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authorMahantesh Kumbar <mkumbar@nvidia.com>2017-02-06 06:19:24 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-10 12:43:46 -0500
commit3885fe099af0bda910ac8ee64f2cd1a5bbea3ab0 (patch)
tree602ead38e7631ce81db7e600802fdac0aba49974 /drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h
parent8da422ac577338ecb2d4114e1d8d5f36cf4cab78 (diff)
gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpu
Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder to support cross platform feature implementation. Made changes to files which accessed “include pmuif/*” to reflect pmuif/* movement changes. Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files. Jira NVGPU-19 Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1299823 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h')
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h434
1 files changed, 0 insertions, 434 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h b/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h
deleted file mode 100644
index b6842fb7..00000000
--- a/drivers/gpu/nvgpu/pmuif/gpmuifpmgr.h
+++ /dev/null
@@ -1,434 +0,0 @@
1/*
2* Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14#ifndef _GPMUIFPMGR_H_
15#define _GPMUIFPMGR_H_
16
17#include "ctrl/ctrlpmgr.h"
18#include "pmuif/gpmuifboardobj.h"
19#include <nvgpu/flcnif_cmn.h>
20
21struct nv_pmu_pmgr_i2c_device_desc {
22 struct nv_pmu_boardobj super;
23 u8 dcb_index;
24 u16 i2c_address;
25 u32 i2c_flags;
26 u8 i2c_port;
27};
28
29#define NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES (32)
30
31struct nv_pmu_pmgr_i2c_device_desc_table {
32 u32 dev_mask;
33 struct nv_pmu_pmgr_i2c_device_desc
34 devices[NV_PMU_PMGR_I2C_DEVICE_DESC_TABLE_MAX_DEVICES];
35};
36
37struct nv_pmu_pmgr_pwr_device_desc {
38 struct nv_pmu_boardobj super;
39 u32 power_corr_factor;
40};
41
42#define NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM 0x03
43
44struct nv_pmu_pmgr_pwr_device_desc_ina3221 {
45 struct nv_pmu_pmgr_pwr_device_desc super;
46 u8 i2c_dev_idx;
47 struct ctrl_pmgr_pwr_device_info_rshunt
48 r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM];
49 u16 configuration;
50 u16 mask_enable;
51 u32 event_mask;
52 u16 curr_correct_m;
53 s16 curr_correct_b;
54};
55
56union nv_pmu_pmgr_pwr_device_desc_union {
57 struct nv_pmu_boardobj board_obj;
58 struct nv_pmu_pmgr_pwr_device_desc pwr_dev;
59 struct nv_pmu_pmgr_pwr_device_desc_ina3221 ina3221;
60};
61
62struct nv_pmu_pmgr_pwr_device_ba_info {
63 bool b_initialized_and_used;
64};
65
66struct nv_pmu_pmgr_pwr_device_desc_table_header {
67 struct nv_pmu_boardobjgrp_e32 super;
68 struct nv_pmu_pmgr_pwr_device_ba_info ba_info;
69};
70
71NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_device_desc_table_header,
72 sizeof(struct nv_pmu_pmgr_pwr_device_desc_table_header));
73NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_device_desc_union,
74 sizeof(union nv_pmu_pmgr_pwr_device_desc_union));
75
76struct nv_pmu_pmgr_pwr_device_desc_table {
77 union nv_pmu_pmgr_pwr_device_desc_table_header_aligned hdr;
78 union nv_pmu_pmgr_pwr_device_desc_union_aligned
79 devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES];
80};
81
82union nv_pmu_pmgr_pwr_device_dmem_size {
83 union nv_pmu_pmgr_pwr_device_desc_table_header_aligned pwr_device_hdr;
84 union nv_pmu_pmgr_pwr_device_desc_union_aligned pwr_device;
85};
86
87struct nv_pmu_pmgr_pwr_channel {
88 struct nv_pmu_boardobj super;
89 u8 pwr_rail;
90 u8 ch_idx;
91 u32 volt_fixedu_v;
92 u32 pwr_corr_slope;
93 s32 pwr_corr_offsetm_w;
94 u32 curr_corr_slope;
95 s32 curr_corr_offsetm_a;
96 u32 dependent_ch_mask;
97};
98
99#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS 16
100
101#define NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS 16
102
103struct nv_pmu_pmgr_pwr_channel_sensor {
104 struct nv_pmu_pmgr_pwr_channel super;
105 u8 pwr_dev_idx;
106 u8 pwr_dev_prov_idx;
107};
108
109struct nv_pmu_pmgr_pwr_channel_pmu_compactible {
110 u8 pmu_compactible_data[56];
111};
112
113union nv_pmu_pmgr_pwr_channel_union {
114 struct nv_pmu_boardobj board_obj;
115 struct nv_pmu_pmgr_pwr_channel pwr_channel;
116 struct nv_pmu_pmgr_pwr_channel_sensor sensor;
117 struct nv_pmu_pmgr_pwr_channel_pmu_compactible pmu_pwr_channel;
118};
119
120#define NV_PMU_PMGR_PWR_MONITOR_TYPE_NO_POLLING 0x02
121
122struct nv_pmu_pmgr_pwr_monitor_pstate {
123 u32 hw_channel_mask;
124};
125
126union nv_pmu_pmgr_pwr_monitor_type_specific {
127 struct nv_pmu_pmgr_pwr_monitor_pstate pstate;
128};
129
130struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible {
131 u8 pmu_compactible_data[28];
132};
133
134union nv_pmu_pmgr_pwr_chrelationship_union {
135 struct nv_pmu_boardobj board_obj;
136 struct nv_pmu_pmgr_pwr_chrelationship_pmu_compactible pmu_pwr_chrelationship;
137};
138
139struct nv_pmu_pmgr_pwr_channel_header {
140 struct nv_pmu_boardobjgrp_e32 super;
141 u8 type;
142 union nv_pmu_pmgr_pwr_monitor_type_specific type_specific;
143 u8 sample_count;
144 u16 sampling_periodms;
145 u16 sampling_period_low_powerms;
146 u32 total_gpu_power_channel_mask;
147 u32 physical_channel_mask;
148};
149
150struct nv_pmu_pmgr_pwr_chrelationship_header {
151 struct nv_pmu_boardobjgrp_e32 super;
152};
153
154NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_channel_header,
155 sizeof(struct nv_pmu_pmgr_pwr_channel_header));
156NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_chrelationship_header,
157 sizeof(struct nv_pmu_pmgr_pwr_chrelationship_header));
158NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_chrelationship_union,
159 sizeof(union nv_pmu_pmgr_pwr_chrelationship_union));
160NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_channel_union,
161 sizeof(union nv_pmu_pmgr_pwr_channel_union));
162
163struct nv_pmu_pmgr_pwr_channel_desc {
164 union nv_pmu_pmgr_pwr_channel_header_aligned hdr;
165 union nv_pmu_pmgr_pwr_channel_union_aligned
166 channels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHANNELS];
167};
168
169struct nv_pmu_pmgr_pwr_chrelationship_desc {
170 union nv_pmu_pmgr_pwr_chrelationship_header_aligned hdr;
171 union nv_pmu_pmgr_pwr_chrelationship_union_aligned
172 ch_rels[NV_PMU_PMGR_PWR_CHANNEL_MAX_CHRELATIONSHIPS];
173};
174
175union nv_pmu_pmgr_pwr_monitor_dmem_size {
176 union nv_pmu_pmgr_pwr_channel_header_aligned channel_hdr;
177 union nv_pmu_pmgr_pwr_channel_union_aligned channel;
178 union nv_pmu_pmgr_pwr_chrelationship_header_aligned ch_rels_hdr;
179 union nv_pmu_pmgr_pwr_chrelationship_union_aligned ch_rels;
180};
181
182struct nv_pmu_pmgr_pwr_monitor_pack {
183 struct nv_pmu_pmgr_pwr_channel_desc channels;
184 struct nv_pmu_pmgr_pwr_chrelationship_desc ch_rels;
185};
186
187#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES 32
188
189#define NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS 32
190
191struct nv_pmu_pmgr_pwr_policy {
192 struct nv_pmu_boardobj super;
193 u8 ch_idx;
194 u8 num_limit_inputs;
195 u8 limit_unit;
196 u8 sample_mult;
197 u32 limit_curr;
198 u32 limit_min;
199 u32 limit_max;
200 struct ctrl_pmgr_pwr_policy_info_integral integral;
201 enum ctrl_pmgr_pwr_policy_filter_type filter_type;
202 union ctrl_pmgr_pwr_policy_filter_param filter_param;
203};
204
205struct nv_pmu_pmgr_pwr_policy_hw_threshold {
206 struct nv_pmu_pmgr_pwr_policy super;
207 u8 threshold_idx;
208 u8 low_threshold_idx;
209 bool b_use_low_threshold;
210 u16 low_threshold_value;
211};
212
213struct nv_pmu_pmgr_pwr_policy_sw_threshold {
214 struct nv_pmu_pmgr_pwr_policy super;
215 u8 threshold_idx;
216 u8 low_threshold_idx;
217 bool b_use_low_threshold;
218 u16 low_threshold_value;
219 u8 event_id;
220};
221
222struct nv_pmu_pmgr_pwr_policy_pmu_compactible {
223 u8 pmu_compactible_data[68];
224};
225
226union nv_pmu_pmgr_pwr_policy_union {
227 struct nv_pmu_boardobj board_obj;
228 struct nv_pmu_pmgr_pwr_policy pwr_policy;
229 struct nv_pmu_pmgr_pwr_policy_hw_threshold hw_threshold;
230 struct nv_pmu_pmgr_pwr_policy_sw_threshold sw_threshold;
231 struct nv_pmu_pmgr_pwr_policy_pmu_compactible pmu_pwr_policy;
232};
233
234struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible {
235 u8 pmu_compactible_data[24];
236};
237
238union nv_pmu_pmgr_pwr_policy_relationship_union {
239 struct nv_pmu_boardobj board_obj;
240 struct nv_pmu_pmgr_pwr_policy_relationship_pmu_compactible pmu_pwr_relationship;
241};
242
243struct nv_pmu_pmgr_pwr_violation_pmu_compactible {
244 u8 pmu_compactible_data[16];
245};
246
247union nv_pmu_pmgr_pwr_violation_union {
248 struct nv_pmu_boardobj board_obj;
249 struct nv_pmu_pmgr_pwr_violation_pmu_compactible violation;
250};
251
252#define NV_PMU_PMGR_PWR_POLICY_DESC_TABLE_VERSION_3X 0x30
253
254NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_union,
255 sizeof(union nv_pmu_pmgr_pwr_policy_union));
256NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_policy_relationship_union,
257 sizeof(union nv_pmu_pmgr_pwr_policy_relationship_union));
258
259#define NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS 2
260
261struct nv_pmu_perf_domain_group_limits
262{
263 u32 values[NV_PMU_PERF_DOMAIN_GROUP_MAX_GROUPS];
264} ;
265
266#define NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT 0x6
267
268struct nv_pmu_pmgr_pwr_policy_desc_header {
269 struct nv_pmu_boardobjgrp_e32 super;
270 u8 version;
271 bool b_enabled;
272 u8 low_sampling_mult;
273 u8 semantic_policy_tbl[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES];
274 u16 base_sample_period;
275 u16 min_client_sample_period;
276 u32 reserved_pmu_policy_mask[NV_PMU_PMGR_RESERVED_PWR_POLICY_MASK_COUNT];
277 struct nv_pmu_perf_domain_group_limits global_ceiling;
278};
279
280NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policy_desc_header ,
281 sizeof(struct nv_pmu_pmgr_pwr_policy_desc_header ));
282
283struct nv_pmu_pmgr_pwr_policyrel_desc_header {
284 struct nv_pmu_boardobjgrp_e32 super;
285};
286
287NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_policyrel_desc_header,
288 sizeof(struct nv_pmu_pmgr_pwr_policyrel_desc_header));
289
290struct nv_pmu_pmgr_pwr_violation_desc_header {
291 struct nv_pmu_boardobjgrp_e32 super;
292};
293
294NV_PMU_MAKE_ALIGNED_STRUCT(nv_pmu_pmgr_pwr_violation_desc_header,
295 sizeof(struct nv_pmu_pmgr_pwr_violation_desc_header));
296NV_PMU_MAKE_ALIGNED_UNION(nv_pmu_pmgr_pwr_violation_union,
297 sizeof(union nv_pmu_pmgr_pwr_violation_union));
298
299struct nv_pmu_pmgr_pwr_policy_desc {
300 union nv_pmu_pmgr_pwr_policy_desc_header_aligned hdr;
301 union nv_pmu_pmgr_pwr_policy_union_aligned
302 policies[NV_PMU_PMGR_PWR_POLICY_MAX_POLICIES];
303};
304
305struct nv_pmu_pmgr_pwr_policyrel_desc {
306 union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned hdr;
307 union nv_pmu_pmgr_pwr_policy_relationship_union_aligned
308 policy_rels[NV_PMU_PMGR_PWR_POLICY_MAX_POLICY_RELATIONSHIPS];
309};
310
311struct nv_pmu_pmgr_pwr_violation_desc {
312 union nv_pmu_pmgr_pwr_violation_desc_header_aligned hdr;
313 union nv_pmu_pmgr_pwr_violation_union_aligned
314 violations[CTRL_PMGR_PWR_VIOLATION_MAX];
315};
316
317union nv_pmu_pmgr_pwr_policy_dmem_size {
318 union nv_pmu_pmgr_pwr_policy_desc_header_aligned policy_hdr;
319 union nv_pmu_pmgr_pwr_policy_union_aligned policy;
320 union nv_pmu_pmgr_pwr_policyrel_desc_header_aligned policy_rels_hdr;
321 union nv_pmu_pmgr_pwr_policy_relationship_union_aligned policy_rels;
322 union nv_pmu_pmgr_pwr_violation_desc_header_aligned violation_hdr;
323 union nv_pmu_pmgr_pwr_violation_union_aligned violation;
324};
325
326struct nv_pmu_pmgr_pwr_policy_pack {
327 struct nv_pmu_pmgr_pwr_policy_desc policies;
328 struct nv_pmu_pmgr_pwr_policyrel_desc policy_rels;
329 struct nv_pmu_pmgr_pwr_violation_desc violations;
330};
331
332#define NV_PMU_PMGR_CMD_ID_SET_OBJECT (0x00000000)
333
334#define NV_PMU_PMGR_MSG_ID_QUERY (0x00000002)
335
336#define NV_PMU_PMGR_CMD_ID_PWR_DEVICES_QUERY (0x00000001)
337
338#define NV_PMU_PMGR_CMD_ID_LOAD (0x00000006)
339
340#define NV_PMU_PMGR_CMD_ID_UNLOAD (0x00000007)
341
342struct nv_pmu_pmgr_cmd_set_object {
343 u8 cmd_type;
344 u8 pad[2];
345 u8 object_type;
346 struct nv_pmu_allocation object;
347};
348
349#define NV_PMU_PMGR_SET_OBJECT_ALLOC_OFFSET (0x04)
350
351#define NV_PMU_PMGR_OBJECT_I2C_DEVICE_DESC_TABLE (0x00000000)
352
353#define NV_PMU_PMGR_OBJECT_PWR_DEVICE_DESC_TABLE (0x00000001)
354
355#define NV_PMU_PMGR_OBJECT_PWR_MONITOR (0x00000002)
356
357#define NV_PMU_PMGR_OBJECT_PWR_POLICY (0x00000005)
358
359struct nv_pmu_pmgr_pwr_devices_query_payload {
360 struct {
361 u32 powerm_w;
362 u32 voltageu_v;
363 u32 currentm_a;
364 } devices[CTRL_PMGR_PWR_DEVICES_MAX_DEVICES];
365};
366
367struct nv_pmu_pmgr_cmd_pwr_devices_query {
368 u8 cmd_type;
369 u8 pad[3];
370 u32 dev_mask;
371 struct nv_pmu_allocation payload;
372};
373
374#define NV_PMU_PMGR_PWR_DEVICES_QUERY_ALLOC_OFFSET (0x08)
375
376struct nv_pmu_pmgr_cmd_load {
377 u8 cmd_type;
378};
379
380struct nv_pmu_pmgr_cmd_unload {
381 u8 cmd_type;
382};
383
384struct nv_pmu_pmgr_cmd {
385 union {
386 u8 cmd_type;
387 struct nv_pmu_pmgr_cmd_set_object set_object;
388 struct nv_pmu_pmgr_cmd_pwr_devices_query pwr_dev_query;
389 struct nv_pmu_pmgr_cmd_load load;
390 struct nv_pmu_pmgr_cmd_unload unload;
391 };
392};
393
394#define NV_PMU_PMGR_MSG_ID_SET_OBJECT (0x00000000)
395
396#define NV_PMU_PMGR_MSG_ID_LOAD (0x00000004)
397
398#define NV_PMU_PMGR_MSG_ID_UNLOAD (0x00000005)
399
400struct nv_pmu_pmgr_msg_set_object {
401 u8 msg_type;
402 bool b_success;
403 flcn_status flcnstatus;
404 u8 object_type;
405};
406
407struct nv_pmu_pmgr_msg_query {
408 u8 msg_type;
409 bool b_success;
410 flcn_status flcnstatus;
411 u8 cmd_type;
412};
413
414struct nv_pmu_pmgr_msg_load {
415 u8 msg_type;
416 bool b_success;
417 flcn_status flcnstatus;
418};
419
420struct nv_pmu_pmgr_msg_unload {
421 u8 msg_type;
422};
423
424struct nv_pmu_pmgr_msg {
425 union {
426 u8 msg_type;
427 struct nv_pmu_pmgr_msg_set_object set_object;
428 struct nv_pmu_pmgr_msg_query query;
429 struct nv_pmu_pmgr_msg_load load;
430 struct nv_pmu_pmgr_msg_unload unload;
431 };
432};
433
434#endif
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