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author | Bharat Nihalani <bnihalani@nvidia.com> | 2016-06-10 08:09:17 -0400 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:17 -0500 |
commit | 4306af531d1e0b68b1b24d9c4a625018461d6d34 (patch) | |
tree | 1900f75ed8d7a9f441846da3f72c3681a4f4bf09 /drivers/gpu/nvgpu/pmuif/gpmuifclk.h | |
parent | ca2c4ce83a846bbab953e91af37c762efaa975e6 (diff) |
WAR: gpu: nvgpu: gp10b: disable railgate for K4.4
This is done to mask a race issue seen where power refcount
is zero during ISR or bottom half.
Bug 200198908
Change-Id: I0a8ed774cd4fda9db65429b5aad03c5e001ff666
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/1162314
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuifclk.h')
0 files changed, 0 insertions, 0 deletions