diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2017-02-06 06:19:24 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-02-10 12:43:46 -0500 |
commit | 3885fe099af0bda910ac8ee64f2cd1a5bbea3ab0 (patch) | |
tree | 602ead38e7631ce81db7e600802fdac0aba49974 /drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h | |
parent | 8da422ac577338ecb2d4114e1d8d5f36cf4cab78 (diff) |
gpu: nvgpu: move pmuif/* to drivers/gpu/nvgpu/include/nvgpu
Moved pmuif/* headers to drivers/gpu/nvgpu/include/nvgpu folder
to support cross platform feature implementation.
Made changes to files which accessed include pmuif/* to reflect
pmuif/* movement changes.
Deleted includes of gk20a.h/pmu_gk20a.h from pmuif/*.h files.
Jira NVGPU-19
Change-Id: Iace4e107c24bdaff08a407eae3b147959173e485
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1299823
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h')
-rw-r--r-- | drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h | 121 |
1 files changed, 0 insertions, 121 deletions
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h deleted file mode 100644 index 1d200129..00000000 --- a/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h +++ /dev/null | |||
@@ -1,121 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _GPMUIFCMN_H_ | ||
14 | #define _GPMUIFCMN_H_ | ||
15 | |||
16 | /* | ||
17 | * Defines the logical queue IDs that must be used when submitting | ||
18 | * commands to the PMU | ||
19 | */ | ||
20 | /* write by sw, read by pmu, protected by sw mutex lock */ | ||
21 | #define PMU_COMMAND_QUEUE_HPQ 0 | ||
22 | /* write by sw, read by pmu, protected by sw mutex lock */ | ||
23 | #define PMU_COMMAND_QUEUE_LPQ 1 | ||
24 | /* read/write by sw/hw, protected by hw pmu mutex, id = 2 */ | ||
25 | #define PMU_COMMAND_QUEUE_BIOS 2 | ||
26 | /* read/write by sw/hw, protected by hw pmu mutex, id = 3 */ | ||
27 | #define PMU_COMMAND_QUEUE_SMI 3 | ||
28 | /* write by pmu, read by sw, accessed by interrupt handler, no lock */ | ||
29 | #define PMU_MESSAGE_QUEUE 4 | ||
30 | #define PMU_QUEUE_COUNT 5 | ||
31 | |||
32 | #define PMU_IS_COMMAND_QUEUE(id) \ | ||
33 | ((id) < PMU_MESSAGE_QUEUE) | ||
34 | |||
35 | #define PMU_IS_SW_COMMAND_QUEUE(id) \ | ||
36 | (((id) == PMU_COMMAND_QUEUE_HPQ) || \ | ||
37 | ((id) == PMU_COMMAND_QUEUE_LPQ)) | ||
38 | |||
39 | #define PMU_IS_MESSAGE_QUEUE(id) \ | ||
40 | ((id) == PMU_MESSAGE_QUEUE) | ||
41 | |||
42 | enum { | ||
43 | OFLAG_READ = 0, | ||
44 | OFLAG_WRITE | ||
45 | }; | ||
46 | |||
47 | #define QUEUE_SET (true) | ||
48 | #define QUEUE_GET (false) | ||
49 | |||
50 | #define QUEUE_ALIGNMENT (4) | ||
51 | |||
52 | /* An enumeration containing all valid logical mutex identifiers */ | ||
53 | enum { | ||
54 | PMU_MUTEX_ID_RSVD1 = 0, | ||
55 | PMU_MUTEX_ID_GPUSER, | ||
56 | PMU_MUTEX_ID_QUEUE_BIOS, | ||
57 | PMU_MUTEX_ID_QUEUE_SMI, | ||
58 | PMU_MUTEX_ID_GPMUTEX, | ||
59 | PMU_MUTEX_ID_I2C, | ||
60 | PMU_MUTEX_ID_RMLOCK, | ||
61 | PMU_MUTEX_ID_MSGBOX, | ||
62 | PMU_MUTEX_ID_FIFO, | ||
63 | PMU_MUTEX_ID_PG, | ||
64 | PMU_MUTEX_ID_GR, | ||
65 | PMU_MUTEX_ID_CLK, | ||
66 | PMU_MUTEX_ID_RSVD6, | ||
67 | PMU_MUTEX_ID_RSVD7, | ||
68 | PMU_MUTEX_ID_RSVD8, | ||
69 | PMU_MUTEX_ID_RSVD9, | ||
70 | PMU_MUTEX_ID_INVALID | ||
71 | }; | ||
72 | |||
73 | #define PMU_MUTEX_ID_IS_VALID(id) \ | ||
74 | ((id) < PMU_MUTEX_ID_INVALID) | ||
75 | |||
76 | #define PMU_INVALID_MUTEX_OWNER_ID (0) | ||
77 | |||
78 | /* | ||
79 | * The PMU's frame-buffer interface block has several slots/indices | ||
80 | * which can be bound to support DMA to various surfaces in memory | ||
81 | */ | ||
82 | enum { | ||
83 | PMU_DMAIDX_UCODE = 0, | ||
84 | PMU_DMAIDX_VIRT = 1, | ||
85 | PMU_DMAIDX_PHYS_VID = 2, | ||
86 | PMU_DMAIDX_PHYS_SYS_COH = 3, | ||
87 | PMU_DMAIDX_PHYS_SYS_NCOH = 4, | ||
88 | PMU_DMAIDX_RSVD = 5, | ||
89 | PMU_DMAIDX_PELPG = 6, | ||
90 | PMU_DMAIDX_END = 7 | ||
91 | }; | ||
92 | |||
93 | /* | ||
94 | * Falcon PMU DMA's minimum size in bytes. | ||
95 | */ | ||
96 | #define PMU_DMA_MIN_READ_SIZE_BYTES 16 | ||
97 | #define PMU_DMA_MIN_WRITE_SIZE_BYTES 4 | ||
98 | |||
99 | #define PMU_FB_COPY_RW_ALIGNMENT \ | ||
100 | ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \ | ||
101 | PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES) | ||
102 | |||
103 | /* | ||
104 | * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned | ||
105 | * data structures to issue DMA read/write operations. | ||
106 | */ | ||
107 | #define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \ | ||
108 | union name##_aligned { \ | ||
109 | struct name data; \ | ||
110 | u8 pad[ALIGN_UP(sizeof(struct name), \ | ||
111 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
112 | } | ||
113 | |||
114 | #define NV_PMU_MAKE_ALIGNED_UNION(name, size) \ | ||
115 | union name##_aligned { \ | ||
116 | union name data; \ | ||
117 | u8 pad[ALIGN_UP(sizeof(union name), \ | ||
118 | (PMU_FB_COPY_RW_ALIGNMENT))]; \ | ||
119 | } | ||
120 | |||
121 | #endif /* _GPMUIFCMN_H_*/ | ||