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| author | Deepak Nibade <dnibade@nvidia.com> | 2017-12-14 08:11:35 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-22 04:04:57 -0500 |
| commit | 8c7626944f280b5c5e04e71210be3241840b4cee (patch) | |
| tree | e9472009c50eb6aa287fa06bd957f2cac097a1d0 /drivers/gpu/nvgpu/pmgr/pwrpolicy.h | |
| parent | 03bcab9730b57e0ea4c121576fa3da6036d20a00 (diff) | |
gpu: nvgpu: use hard coded tpc count mask
In gr_gv11b_set_gpc_tpc_mask(), we calculate tpc_count_mask based on
number of TPCs
But since we could change number of TPCs runtime, we would end up
calulating incorrect tpc_count_mask
Hence instead of calculating tpc_count_mask, just hard code it to
width of fuse register i.e. hard code tpc_count_mask to 4-bit value
Bug 2031635
Change-Id: Ia6f74d39d066775a5d133897305554df1e54157e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1617917
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.h')
0 files changed, 0 insertions, 0 deletions