diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/pmgr/pwrpolicy.h | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.h')
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrpolicy.h | 127 |
1 files changed, 127 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h new file mode 100644 index 00000000..008282d3 --- /dev/null +++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h | |||
@@ -0,0 +1,127 @@ | |||
1 | /* | ||
2 | * general power channel structures & definitions | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _PWRPOLICY_H_ | ||
16 | #define _PWRPOLICY_H_ | ||
17 | |||
18 | #include "boardobj/boardobjgrp.h" | ||
19 | #include "boardobj/boardobj.h" | ||
20 | #include "pmuif/gpmuifpmgr.h" | ||
21 | #include "ctrl/ctrlpmgr.h" | ||
22 | |||
23 | #define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4 | ||
24 | |||
25 | enum pwr_policy_limit_id { | ||
26 | PWR_POLICY_LIMIT_ID_MIN = 0x00000000, | ||
27 | PWR_POLICY_LIMIT_ID_RATED, | ||
28 | PWR_POLICY_LIMIT_ID_MAX, | ||
29 | PWR_POLICY_LIMIT_ID_CURR, | ||
30 | PWR_POLICY_LIMIT_ID_BATT, | ||
31 | }; | ||
32 | |||
33 | struct pwr_policy { | ||
34 | struct boardobj super; | ||
35 | u8 ch_idx; | ||
36 | u8 num_limit_inputs; | ||
37 | u8 limit_unit; | ||
38 | s32 limit_delta; | ||
39 | u32 limit_min; | ||
40 | u32 limit_rated; | ||
41 | u32 limit_max; | ||
42 | u32 limit_batt; | ||
43 | struct ctrl_pmgr_pwr_policy_info_integral integral; | ||
44 | struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_min; | ||
45 | struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_rated; | ||
46 | struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_max; | ||
47 | struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_batt; | ||
48 | struct ctrl_pmgr_pwr_policy_limit_arbitration limit_arb_curr; | ||
49 | u8 sample_mult; | ||
50 | enum ctrl_pmgr_pwr_policy_filter_type filter_type; | ||
51 | union ctrl_pmgr_pwr_policy_filter_param filter_param; | ||
52 | }; | ||
53 | |||
54 | struct pwr_policy_ext_limit { | ||
55 | u8 policy_table_idx; | ||
56 | u32 limit; | ||
57 | }; | ||
58 | |||
59 | struct pwr_policy_batt_workitem { | ||
60 | u32 power_state; | ||
61 | bool b_full_deflection; | ||
62 | }; | ||
63 | |||
64 | struct pwr_policy_client_workitem { | ||
65 | u32 limit; | ||
66 | bool b_pending; | ||
67 | }; | ||
68 | |||
69 | struct pwr_policy_relationship { | ||
70 | struct boardobj super; | ||
71 | u8 policy_idx; | ||
72 | }; | ||
73 | |||
74 | struct pmgr_pwr_policy { | ||
75 | u8 version; | ||
76 | bool b_enabled; | ||
77 | struct nv_pmu_perf_domain_group_limits global_ceiling; | ||
78 | u8 policy_idxs[CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES]; | ||
79 | struct pwr_policy_ext_limit ext_limits[PWR_POLICY_EXT_POWER_STATE_ID_COUNT]; | ||
80 | s32 ext_power_state; | ||
81 | u16 base_sample_period; | ||
82 | u16 min_client_sample_period; | ||
83 | u8 low_sampling_mult; | ||
84 | struct boardobjgrp_e32 pwr_policies; | ||
85 | struct boardobjgrp_e32 pwr_policy_rels; | ||
86 | struct boardobjgrp_e32 pwr_violations; | ||
87 | struct pwr_policy_client_workitem client_work_item; | ||
88 | }; | ||
89 | |||
90 | struct pwr_policy_limit { | ||
91 | struct pwr_policy super; | ||
92 | }; | ||
93 | |||
94 | struct pwr_policy_hw_threshold { | ||
95 | struct pwr_policy_limit super; | ||
96 | u8 threshold_idx; | ||
97 | u8 low_threshold_idx; | ||
98 | bool b_use_low_threshold; | ||
99 | u16 low_threshold_value; | ||
100 | }; | ||
101 | |||
102 | struct pwr_policy_sw_threshold { | ||
103 | struct pwr_policy_limit super; | ||
104 | u8 threshold_idx; | ||
105 | u8 low_threshold_idx; | ||
106 | bool b_use_low_threshold; | ||
107 | u16 low_threshold_value; | ||
108 | u8 event_id; | ||
109 | }; | ||
110 | |||
111 | union pwr_policy_data_union { | ||
112 | struct boardobj boardobj; | ||
113 | struct pwr_policy pwrpolicy; | ||
114 | struct pwr_policy_hw_threshold hw_threshold; | ||
115 | struct pwr_policy_sw_threshold sw_threshold; | ||
116 | } ; | ||
117 | |||
118 | #define PMGR_GET_PWR_POLICY(g, policy_idx) \ | ||
119 | ((struct pwr_policy *)BOARDOBJGRP_OBJ_GET_BY_IDX( \ | ||
120 | &(g->pmgr_pmu.pmgr_policyobjs.pwr_policies.super), (policy_idx))) | ||
121 | |||
122 | #define PMGR_PWR_POLICY_INCREMENT_LIMIT_INPUT_COUNT(ppolicy) \ | ||
123 | ((ppolicy)->num_limit_inputs++) | ||
124 | |||
125 | u32 pmgr_policy_sw_setup(struct gk20a *g); | ||
126 | |||
127 | #endif | ||