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| author | Seema Khowala <seemaj@nvidia.com> | 2017-03-01 18:24:17 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-20 19:39:49 -0400 |
| commit | 50f371f891c889c782187036c31132fa94c573ac (patch) | |
| tree | bb4be977c782d5a3c2db1e39c0690117871b43dd /drivers/gpu/nvgpu/pmgr/pwrpolicy.h | |
| parent | 38d90b60922e6de6b795694d3e3cdf66d4ddae5f (diff) | |
gpu: nvgpu: add fifo ops for intr_0_error_mask
This change is required to support t19x mmu fault
Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313482
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.h')
0 files changed, 0 insertions, 0 deletions