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| author | Deepak Nibade <dnibade@nvidia.com> | 2018-06-08 00:01:58 -0400 |
|---|---|---|
| committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:08 -0400 |
| commit | 9c5bcbe6f2b71592c3a07d5884b68ad10fdffffd (patch) | |
| tree | 2d42e8c7de8bca04ea852296e51c2b4b97293002 /drivers/gpu/nvgpu/pmgr/pwrpolicy.c | |
| parent | 4e66f214fc03f088b13e1f1cdc097df67dd2c062 (diff) | |
gpu: nvgpu: Add HALs for mmu_fault setup and info
Add below HALs to setup mmu_fault configuration registers and to read
information registers and set them on Volta
gops.fb.write_mmu_fault_buffer_lo_hi()
gops.fb.write_mmu_fault_buffer_get()
gops.fb.write_mmu_fault_buffer_size()
gops.fb.write_mmu_fault_status()
gops.fb.read_mmu_fault_buffer_get()
gops.fb.read_mmu_fault_buffer_put()
gops.fb.read_mmu_fault_buffer_size()
gops.fb.read_mmu_fault_addr_lo_hi()
gops.fb.read_mmu_fault_inst_lo_hi()
gops.fb.read_mmu_fault_info()
gops.fb.read_mmu_fault_status()
Jira NVGPUT-13
Change-Id: Ia99568ff905ada3c035efb4565613576012f5bef
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1744063
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.c')
0 files changed, 0 insertions, 0 deletions