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| author | Tejal Kudav <tkudav@nvidia.com> | 2018-04-02 06:17:38 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-18 02:34:28 -0400 |
| commit | 6a43e51ee362bbf61ca35cda75f31ed3f01862ed (patch) | |
| tree | f807210e0c08c9a7e6ccf67c4044368058ac2712 /drivers/gpu/nvgpu/pmgr/pwrpolicy.c | |
| parent | a807cf20419af737a79a3d0c7fcc1068ac6b724a (diff) | |
gpu: nvgpu: Update gv100 nvlink TLC buffer config
TLC buffer sizes and credit init values do not match with
the values recommended by IAS for dGPU-Xavier configuration.
These buffer configuration values affect the latency over link.
JIRA NVLINK-158
Change-Id: I7822747cb0ae5a5efdd2d57e2104d0cb30bf9352
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1686601
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.c')
0 files changed, 0 insertions, 0 deletions