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| author | Alex Frid <afrid@nvidia.com> | 2017-04-11 22:40:39 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-20 19:14:27 -0400 |
| commit | 11278b0956f0e19b07cc23524dd5c45755a48c5d (patch) | |
| tree | 3d436a7c8fab54fdb1e67510309e299a023cbe30 /drivers/gpu/nvgpu/pmgr/pwrpolicy.c | |
| parent | 7ff9bb2c71186bd721b31f6c74f4010d723ca816 (diff) | |
gpu: nvgpu: Add support for GM20B GPC PLL C1 rev
Separated parameters for GM20B GPC PLL revisions B1 (default), and C1
(new, not characterized, yet). For now, used C1 spec settings.
Skipped PL divider glitch WAR, since revision C1 is glitchless.
Bug 1851797
Bug 1867980
Change-Id: I12dc101d002a41230e9323c47af234f6bae8e034
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/1461680
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrpolicy.c')
0 files changed, 0 insertions, 0 deletions