gpu: nvgpu: cleanup return types for MISRA 10.3

This is a big cleanup of return types across a number of modules in the
nvgpu driver. Many functions were returning u32 but using negative
return codes. This is a MISRA 10.3 violation by assigning signed values
to a u32.

JIRA NVGPU-647

Change-Id: I59ee66706321f5b5b1a07ed8c24b81583e9ba28c
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810743
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
index 4f094c3e..da52b08a 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h
@@ -1,7 +1,7 @@
 /*
  * general power channel structures & definitions
  *
- * Copyright (c) 2016-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2016-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -64,6 +64,6 @@ struct pmgr_pwr_monitor {
         ((struct pwr_channel *)BOARDOBJGRP_OBJ_GET_BY_IDX(                                 \
                 &(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super), (channel_idx)))
 
-u32 pmgr_monitor_sw_setup(struct gk20a *g);
+int pmgr_monitor_sw_setup(struct gk20a *g);
 
 #endif