diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/pmgr/pwrmonitor.h | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrmonitor.h')
-rw-r--r-- | drivers/gpu/nvgpu/pmgr/pwrmonitor.h | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.h b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h new file mode 100644 index 00000000..7cd6b8c9 --- /dev/null +++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.h | |||
@@ -0,0 +1,60 @@ | |||
1 | /* | ||
2 | * general power channel structures & definitions | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | #ifndef _PWRMONITOR_H_ | ||
16 | #define _PWRMONITOR_H_ | ||
17 | |||
18 | #include "boardobj/boardobjgrp.h" | ||
19 | #include "boardobj/boardobj.h" | ||
20 | #include "pmuif/gpmuifpmgr.h" | ||
21 | #include "ctrl/ctrlpmgr.h" | ||
22 | |||
23 | struct pwr_channel { | ||
24 | struct boardobj super; | ||
25 | u8 pwr_rail; | ||
26 | u32 volt_fixed_uv; | ||
27 | u32 pwr_corr_slope; | ||
28 | s32 pwr_corr_offset_mw; | ||
29 | u32 curr_corr_slope; | ||
30 | s32 curr_corr_offset_ma; | ||
31 | u32 dependent_ch_mask; | ||
32 | }; | ||
33 | |||
34 | struct pwr_chrelationship { | ||
35 | struct boardobj super; | ||
36 | u8 chIdx; | ||
37 | }; | ||
38 | |||
39 | struct pwr_channel_sensor { | ||
40 | struct pwr_channel super; | ||
41 | u8 pwr_dev_idx; | ||
42 | u8 pwr_dev_prov_idx; | ||
43 | }; | ||
44 | |||
45 | struct pmgr_pwr_monitor { | ||
46 | bool b_is_topology_tbl_ver_1x; | ||
47 | struct boardobjgrp_e32 pwr_channels; | ||
48 | struct boardobjgrp_e32 pwr_ch_rels; | ||
49 | u8 total_gpu_channel_idx; | ||
50 | u32 physical_channel_mask; | ||
51 | struct nv_pmu_pmgr_pwr_monitor_pack pmu_data; | ||
52 | }; | ||
53 | |||
54 | #define PMGR_PWR_MONITOR_GET_PWR_CHANNEL(g, channel_idx) \ | ||
55 | ((struct pwr_channel *)BOARDOBJGRP_OBJ_GET_BY_IDX( \ | ||
56 | &(g->pmgr_pmu.pmgr_monitorobjs.pwr_channels.super), (channel_idx))) | ||
57 | |||
58 | u32 pmgr_monitor_sw_setup(struct gk20a *g); | ||
59 | |||
60 | #endif | ||