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| author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-08-25 18:39:14 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-31 13:33:48 -0500 |
| commit | dddeee54b640e4c28866354b7f2e4edd907e3344 (patch) | |
| tree | c98de41b1702f66734a836bca8e6c5d9288de4d1 /drivers/gpu/nvgpu/pmgr/pwrdev.h | |
| parent | 9cba01592b5b0aec595823c3062510ee08e2f8e1 (diff) | |
gpu: nvgpu: Fix priv ring error detection
Use hardware headers instead of hardcoded register numbers in priv
ring. This required updating the priv ring headers to add all the
registers and fields needed.
Incidentally this also gets rid of a lot of GPC priv ring registers
as they're not used in our code.
Also delete duplicate prints for the same information. We were
dumping GPC error also in gk20a_pbus_isr(), and we dumped master
information twice.
Dump status of each GPC separately instead of supporting only GPC0.
Change-Id: Ic50817ecc50892618fa27947fa83b05148b2cd6a
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1295481
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pwrdev.h')
0 files changed, 0 insertions, 0 deletions