gpu: nvgpu: Add pmgr support

This CL covers the following implementation,
1) Power Sensor Table parsing.
2) Power Topology Table parsing.
3) Add debugfs interface to get the current power(mW), current(mA) and
   voltage(uV) information from PMU.
4) Power Policy Table Parsing
5) Implement PMU boardobj interface for pmgr module.
6) Over current protection.

JIRA DNVGPU-47

Change-Id: I7b1eefacc4f0a9824ab94ec8dcebefe81b7660d3
Signed-off-by: Lakshmanan M <lm@nvidia.com>
Reviewed-on: http://git-master/r/1217189
(cherry picked from commit ecd0b16316cb4110118c6677f5f03e02921c29b6)
Reviewed-on: http://git-master/r/1241953
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit

1 files changed, 51 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.h b/drivers/gpu/nvgpu/pmgr/pwrdev.h
new file mode 100644
index 00000000..b8592a18
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.h
@@ -0,0 +1,51 @@
+/*
+ * general power device structures & definitions
+ *
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _PWRDEV_H_
+#define _PWRDEV_H_
+
+#include "boardobj/boardobj.h"
+#include "pmuif/gpmuifpmgr.h"
+#include "ctrl/ctrlpmgr.h"
+
+#define  PWRDEV_I2CDEV_DEVICE_INDEX_NONE  (0xFF)
+
+#define  PWR_DEVICE_PROV_NUM_DEFAULT                                           1
+
+struct pwr_device {
+        struct boardobj super;
+        u8 power_rail;
+        u8 i2c_dev_idx;
+        bool bIs_inforom_config;
+        u32 power_corr_factor;
+};
+
+struct pwr_devices {
+        struct boardobjgrp_e32 super;
+};
+
+struct pwr_device_ina3221 {
+        struct pwr_device super;
+        struct ctrl_pmgr_pwr_device_info_rshunt
+                r_shuntm_ohm[NV_PMU_PMGR_PWR_DEVICE_INA3221_CH_NUM];
+        u16 configuration;
+        u16 mask_enable;
+        u8 gpio_function;
+        u16 curr_correct_m;
+        s16 curr_correct_b;
+} ;
+
+u32 pmgr_device_sw_setup(struct gk20a *g);
+
+#endif