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authorsmadhavan <smadhavan@nvidia.com>2018-09-11 01:01:06 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-19 05:38:29 -0400
commit2805f03aa0496502b64ff760f667bfe9d8a27928 (patch)
tree307dc9eaa38757a17c71d86c9b648be426a9b16e /drivers/gpu/nvgpu/pmgr/pmgrpmu.h
parentfbc5296e7d8a7eeceba9a904dd4736373c4c6d4e (diff)
nvgpu: pmgr: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with an underscore. These leading underscores are to be removed from the macro names. This patch will fix such violations in pmgr by renaming them to follow the convention, 'NVGPU_PARENT-DIR_HEADER-NAME' when there is no keyword repetition between file name and directory or 'NVGPU_HEADER-NAME' when there is repetition. JIRA NVGPU-1028 Change-Id: I1beda400163bfc6278763161520f918fb4a3d096 Signed-off-by: smadhavan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1815663 Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pmgr/pmgrpmu.h')
-rw-r--r--drivers/gpu/nvgpu/pmgr/pmgrpmu.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h
index 23062b13..f4ffaef3 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.h
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.h
@@ -21,8 +21,8 @@
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE. 22 * DEALINGS IN THE SOFTWARE.
23 */ 23 */
24#ifndef _PMGRPMU_H_ 24#ifndef NVGPU_PMGRPMU_H
25#define _PMGRPMU_H_ 25#define NVGPU_PMGRPMU_H
26 26
27#include <nvgpu/gk20a.h> 27#include <nvgpu/gk20a.h>
28 28
@@ -36,4 +36,4 @@ u32 pmgr_pmu_pwr_devices_query_blocking(
36 u32 pwr_dev_mask, 36 u32 pwr_dev_mask,
37 struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload); 37 struct nv_pmu_pmgr_pwr_devices_query_payload *ppayload);
38 38
39#endif 39#endif /* NVGPU_PMGRPMU_H */