gpu: nvgpu: Expose boot freq as max freq for dGPU

On dGPU so far we boot only at maximum GPC2CLK frequency. Expose that
as maximum clock rate to user space.

Bug 200251486

Change-Id: Ie3463782a0e36028074325ce652c7ef554f6ea2c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1252907
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Shreshtha Sahu <ssahu@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

1 files changed, 14 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/pci.c b/drivers/gpu/nvgpu/pci.c
index 3c46f073..c3617789 100644
--- a/drivers/gpu/nvgpu/pci.c
+++ b/drivers/gpu/nvgpu/pci.c
@@ -21,6 +21,7 @@
 #include "nvgpu_common.h"
 #include "gk20a/gk20a.h"
 #include "gk20a/platform_gk20a.h"
+#include "clk/clk.h"
 
 #define PCI_INTERFACE_NAME "card-%s%%s"
 
@@ -39,6 +40,16 @@ static bool nvgpu_pci_tegra_is_railgated(struct device *pdev)
         return false;
 }
 
+static long nvgpu_pci_clk_round_rate(struct device *dev, unsigned long rate)
+{
+        long ret = (long)rate;
+
+        if (rate == UINT_MAX)
+                ret = BOOT_GPC2CLK_MHZ * 1000000UL;
+
+        return ret;
+}
+
 static struct gk20a_platform nvgpu_pci_device[] = {
         { /* DEVICE=0x1c35 */
         /* ptimer src frequency in hz */
@@ -57,6 +68,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 
         /* power management callbacks */
         .is_railgated = nvgpu_pci_tegra_is_railgated,
+        .clk_round_rate = nvgpu_pci_clk_round_rate,
 
         .default_big_page_size  = SZ_64K,
 
@@ -84,6 +96,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 
         /* power management callbacks */
         .is_railgated = nvgpu_pci_tegra_is_railgated,
+        .clk_round_rate = nvgpu_pci_clk_round_rate,
 
         .default_big_page_size  = SZ_64K,
 
@@ -111,6 +124,7 @@ static struct gk20a_platform nvgpu_pci_device[] = {
 
         /* power management callbacks */
         .is_railgated = nvgpu_pci_tegra_is_railgated,
+        .clk_round_rate = nvgpu_pci_clk_round_rate,
 
         .default_big_page_size  = SZ_64K,