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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-03-24 12:39:12 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-18 18:04:34 -0400
commit03e7ef2657b4de22eff521b3e44fc4ed5cdf4dca (patch)
tree365bd18b7f633a3fa1139a00eea6da926846fa0e /drivers/gpu/nvgpu/pci.c
parentcb283956b88b312e6621fb22d0a36bf1870d9d21 (diff)
gpu: nvgpu: Move Linux kernel driver code to module.c
Move Linux driver specific code to common/linux/module.c. This includes module initialization, power management, and interrupt functions. Move pci.c, pci.h and nvgpu_common.c under common/linux as they're Linux only files. JIRA NVGPU-16 Change-Id: If92b4dd78ebc0c2bbfa9fbca258e9552e4979b4b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1456162 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/pci.c')
-rw-r--r--drivers/gpu/nvgpu/pci.c510
1 files changed, 0 insertions, 510 deletions
diff --git a/drivers/gpu/nvgpu/pci.c b/drivers/gpu/nvgpu/pci.c
deleted file mode 100644
index fb54ae18..00000000
--- a/drivers/gpu/nvgpu/pci.c
+++ /dev/null
@@ -1,510 +0,0 @@
1/*
2 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <linux/pci.h>
18#include <linux/interrupt.h>
19#include <linux/pm_runtime.h>
20
21#include <nvgpu/nvgpu_common.h>
22#include <nvgpu/kmem.h>
23
24#include "gk20a/gk20a.h"
25#include "gk20a/platform_gk20a.h"
26#include "clk/clk.h"
27
28#include "pci.h"
29
30#define PCI_INTERFACE_NAME "card-%s%%s"
31
32static int nvgpu_pci_tegra_probe(struct device *dev)
33{
34 return 0;
35}
36
37static int nvgpu_pci_tegra_remove(struct device *dev)
38{
39 return 0;
40}
41
42static bool nvgpu_pci_tegra_is_railgated(struct device *pdev)
43{
44 return false;
45}
46
47static long nvgpu_pci_clk_round_rate(struct device *dev, unsigned long rate)
48{
49 long ret = (long)rate;
50
51 if (rate == UINT_MAX)
52 ret = BOOT_GPC2CLK_MHZ * 1000000UL;
53
54 return ret;
55}
56
57static struct gk20a_platform nvgpu_pci_device[] = {
58 { /* DEVICE=0x1c35 */
59 /* ptimer src frequency in hz */
60 .ptimer_src_freq = 31250000,
61
62 .probe = nvgpu_pci_tegra_probe,
63 .remove = nvgpu_pci_tegra_remove,
64
65 /* power management configuration */
66 .railgate_delay = 500,
67 .can_railgate = false,
68 .can_elpg = true,
69 .enable_elpg = true,
70 .enable_elcg = false,
71 .enable_slcg = true,
72 .enable_blcg = true,
73 .enable_mscg = true,
74 .default_pri_timeout = 0x3ff,
75
76 .disable_aspm = true,
77
78 /* power management callbacks */
79 .is_railgated = nvgpu_pci_tegra_is_railgated,
80 .clk_round_rate = nvgpu_pci_clk_round_rate,
81
82 .default_big_page_size = SZ_64K,
83
84 .ch_wdt_timeout_ms = 7000,
85
86 .vidmem_is_vidmem = true,
87 .vbios_min_version = 0x86063000,
88 .hardcode_sw_threshold = true,
89 .ina3221_dcb_index = 0,
90 .ina3221_i2c_address = 0x84,
91 },
92 { /* DEVICE=0x1c36 */
93 /* ptimer src frequency in hz */
94 .ptimer_src_freq = 31250000,
95
96 .probe = nvgpu_pci_tegra_probe,
97 .remove = nvgpu_pci_tegra_remove,
98
99 /* power management configuration */
100 .railgate_delay = 500,
101 .can_railgate = false,
102 .can_elpg = true,
103 .enable_elpg = true,
104 .enable_elcg = false,
105 .enable_slcg = true,
106 .enable_blcg = true,
107 .enable_mscg = true,
108 .default_pri_timeout = 0x3ff,
109
110 .disable_aspm = true,
111
112 /* power management callbacks */
113 .is_railgated = nvgpu_pci_tegra_is_railgated,
114 .clk_round_rate = nvgpu_pci_clk_round_rate,
115
116 .default_big_page_size = SZ_64K,
117
118 .ch_wdt_timeout_ms = 7000,
119
120 .vidmem_is_vidmem = true,
121 .vbios_min_version = 0x86062d00,
122 .hardcode_sw_threshold = true,
123 .ina3221_dcb_index = 0,
124 .ina3221_i2c_address = 0x84,
125 },
126 { /* DEVICE=0x1c37 */
127 /* ptimer src frequency in hz */
128 .ptimer_src_freq = 31250000,
129
130 .probe = nvgpu_pci_tegra_probe,
131 .remove = nvgpu_pci_tegra_remove,
132
133 /* power management configuration */
134 .railgate_delay = 500,
135 .can_railgate = false,
136 .can_elpg = true,
137 .enable_elpg = true,
138 .enable_elcg = false,
139 .enable_slcg = true,
140 .enable_blcg = true,
141 .enable_mscg = true,
142 .default_pri_timeout = 0x3ff,
143
144 .disable_aspm = true,
145
146 /* power management callbacks */
147 .is_railgated = nvgpu_pci_tegra_is_railgated,
148 .clk_round_rate = nvgpu_pci_clk_round_rate,
149
150 .default_big_page_size = SZ_64K,
151
152 .ch_wdt_timeout_ms = 7000,
153
154 .vidmem_is_vidmem = true,
155 .vbios_min_version = 0x86063000,
156 .hardcode_sw_threshold = true,
157 .ina3221_dcb_index = 0,
158 .ina3221_i2c_address = 0x84,
159 },
160 { /* DEVICE=0x1c75 */
161 /* ptimer src frequency in hz */
162 .ptimer_src_freq = 31250000,
163
164 .probe = nvgpu_pci_tegra_probe,
165 .remove = nvgpu_pci_tegra_remove,
166
167 /* power management configuration */
168 .railgate_delay = 500,
169 .can_railgate = false,
170 .can_elpg = true,
171 .enable_elpg = true,
172 .enable_elcg = false,
173 .enable_slcg = true,
174 .enable_blcg = true,
175 .enable_mscg = true,
176 .default_pri_timeout = 0x3ff,
177
178 .disable_aspm = true,
179
180 /* power management callbacks */
181 .is_railgated = nvgpu_pci_tegra_is_railgated,
182 .clk_round_rate = nvgpu_pci_clk_round_rate,
183
184 .default_big_page_size = SZ_64K,
185
186 .ch_wdt_timeout_ms = 7000,
187
188 .vidmem_is_vidmem = true,
189 .vbios_min_version = 0x86064700,
190 .hardcode_sw_threshold = false,
191 .ina3221_dcb_index = 1,
192 .ina3221_i2c_address = 0x80,
193 }
194};
195
196static struct pci_device_id nvgpu_pci_table[] = {
197 {
198 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c35),
199 .class = PCI_BASE_CLASS_DISPLAY << 16,
200 .class_mask = 0xff << 16,
201 .driver_data = 0,
202 },
203 {
204 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c36),
205 .class = PCI_BASE_CLASS_DISPLAY << 16,
206 .class_mask = 0xff << 16,
207 .driver_data = 1,
208 },
209 {
210 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c37),
211 .class = PCI_BASE_CLASS_DISPLAY << 16,
212 .class_mask = 0xff << 16,
213 .driver_data = 2,
214 },
215 {
216 PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, 0x1c75),
217 .class = PCI_BASE_CLASS_DISPLAY << 16,
218 .class_mask = 0xff << 16,
219 .driver_data = 3,
220 },
221 {}
222};
223
224static irqreturn_t nvgpu_pci_isr(int irq, void *dev_id)
225{
226 struct gk20a *g = dev_id;
227 irqreturn_t ret_stall;
228 irqreturn_t ret_nonstall;
229
230 ret_stall = g->ops.mc.isr_stall(g);
231 ret_nonstall = g->ops.mc.isr_nonstall(g);
232
233#if defined(CONFIG_PCI_MSI)
234 /* Send MSI EOI */
235 if (g->ops.xve.rearm_msi && g->msi_enabled)
236 g->ops.xve.rearm_msi(g);
237#endif
238
239 return (ret_stall == IRQ_NONE) ? ret_nonstall : IRQ_WAKE_THREAD;
240}
241
242static irqreturn_t nvgpu_pci_intr_thread(int irq, void *dev_id)
243{
244 struct gk20a *g = dev_id;
245
246 g->ops.mc.isr_thread_stall(g);
247
248 return IRQ_HANDLED;
249}
250
251static int nvgpu_pci_init_support(struct pci_dev *pdev)
252{
253 int err = 0;
254 struct gk20a *g = get_gk20a(&pdev->dev);
255
256 g->regs = ioremap(pci_resource_start(pdev, 0),
257 pci_resource_len(pdev, 0));
258 if (IS_ERR(g->regs)) {
259 nvgpu_err(g, "failed to remap gk20a registers");
260 err = PTR_ERR(g->regs);
261 goto fail;
262 }
263
264 g->bar1 = ioremap(pci_resource_start(pdev, 1),
265 pci_resource_len(pdev, 1));
266 if (IS_ERR(g->bar1)) {
267 nvgpu_err(g, "failed to remap gk20a bar1");
268 err = PTR_ERR(g->bar1);
269 goto fail;
270 }
271
272 return 0;
273
274 fail:
275 return err;
276}
277
278static char *nvgpu_pci_devnode(struct device *dev, umode_t *mode)
279{
280 if (mode)
281 *mode = S_IRUGO | S_IWUGO;
282 return kasprintf(GFP_KERNEL, "nvgpu-pci/%s", dev_name(dev));
283}
284
285static struct class nvgpu_pci_class = {
286 .owner = THIS_MODULE,
287 .name = "nvidia-pci-gpu",
288 .devnode = nvgpu_pci_devnode,
289};
290
291#ifdef CONFIG_PM
292static int nvgpu_pci_pm_runtime_resume(struct device *dev)
293{
294 return gk20a_pm_finalize_poweron(dev);
295}
296
297static int nvgpu_pci_pm_runtime_suspend(struct device *dev)
298{
299 return 0;
300}
301
302static const struct dev_pm_ops nvgpu_pci_pm_ops = {
303 .runtime_resume = nvgpu_pci_pm_runtime_resume,
304 .runtime_suspend = nvgpu_pci_pm_runtime_suspend,
305 .resume = nvgpu_pci_pm_runtime_resume,
306 .suspend = nvgpu_pci_pm_runtime_suspend,
307};
308#endif
309
310static int nvgpu_pci_pm_init(struct device *dev)
311{
312#ifdef CONFIG_PM
313 struct gk20a_platform *platform = gk20a_get_platform(dev);
314
315 if (!platform->can_railgate) {
316 pm_runtime_disable(dev);
317 } else {
318 if (platform->railgate_delay)
319 pm_runtime_set_autosuspend_delay(dev,
320 platform->railgate_delay);
321
322 /*
323 * Runtime PM for PCI devices is disabled by default,
324 * so we need to enable it first
325 */
326 pm_runtime_use_autosuspend(dev);
327 pm_runtime_put_noidle(dev);
328 pm_runtime_allow(dev);
329 }
330#endif
331 return 0;
332}
333
334static int nvgpu_pci_probe(struct pci_dev *pdev,
335 const struct pci_device_id *pent)
336{
337 struct gk20a_platform *platform = NULL;
338 struct gk20a *g;
339 int err;
340 char nodefmt[64];
341
342 /* make sure driver_data is a sane index */
343 if (pent->driver_data >= sizeof(nvgpu_pci_device) /
344 sizeof(nvgpu_pci_device[0])) {
345 return -EINVAL;
346 }
347
348 platform = &nvgpu_pci_device[pent->driver_data];
349 pci_set_drvdata(pdev, platform);
350
351 g = kzalloc(sizeof(struct gk20a), GFP_KERNEL);
352 if (!g) {
353 nvgpu_err(g, "couldn't allocate gk20a support");
354 return -ENOMEM;
355 }
356
357 platform->g = g;
358 g->dev = &pdev->dev;
359
360 nvgpu_kmem_init(g);
361
362 err = pci_enable_device(pdev);
363 if (err)
364 return err;
365 pci_set_master(pdev);
366
367 g->pci_vendor_id = pdev->vendor;
368 g->pci_device_id = pdev->device;
369 g->pci_subsystem_vendor_id = pdev->subsystem_vendor;
370 g->pci_subsystem_device_id = pdev->subsystem_device;
371 g->pci_class = (pdev->class >> 8) & 0xFFFFU; // we only want base/sub
372 g->pci_revision = pdev->revision;
373
374#if defined(CONFIG_PCI_MSI)
375 err = pci_enable_msi(pdev);
376 if (err) {
377 nvgpu_err(g,
378 "MSI could not be enabled, falling back to legacy");
379 g->msi_enabled = false;
380 } else
381 g->msi_enabled = true;
382#endif
383
384 g->irq_stall = pdev->irq;
385 g->irq_nonstall = pdev->irq;
386 if (g->irq_stall < 0)
387 return -ENXIO;
388
389 err = devm_request_threaded_irq(&pdev->dev,
390 g->irq_stall,
391 nvgpu_pci_isr,
392 nvgpu_pci_intr_thread,
393#if defined(CONFIG_PCI_MSI)
394 g->msi_enabled ? 0 :
395#endif
396 IRQF_SHARED, "nvgpu", g);
397 if (err) {
398 nvgpu_err(g,
399 "failed to request irq @ %d", g->irq_stall);
400 return err;
401 }
402 disable_irq(g->irq_stall);
403
404 /*
405 * is_fmodel needs to be in gk20a struct for deferred teardown
406 */
407 g->is_fmodel = platform->is_fmodel;
408
409 err = nvgpu_pci_init_support(pdev);
410 if (err)
411 return err;
412
413 if (strchr(dev_name(&pdev->dev), '%')) {
414 nvgpu_err(g, "illegal character in device name");
415 return -EINVAL;
416 }
417
418 snprintf(nodefmt, sizeof(nodefmt),
419 PCI_INTERFACE_NAME, dev_name(&pdev->dev));
420
421 err = nvgpu_probe(g, "gpu_pci", nodefmt, &nvgpu_pci_class);
422 if (err)
423 return err;
424
425 err = nvgpu_pci_pm_init(&pdev->dev);
426 if (err) {
427 nvgpu_err(g, "pm init failed");
428 return err;
429 }
430
431 g->mm.has_physical_mode = false;
432
433 return 0;
434}
435
436static void nvgpu_pci_remove(struct pci_dev *pdev)
437{
438 struct gk20a_platform *platform = gk20a_get_platform(&pdev->dev);
439 struct gk20a *g = get_gk20a(&pdev->dev);
440
441 gk20a_dbg(gpu_dbg_shutdown, "Removing nvgpu driver!\n");
442
443 if (g->irqs_enabled)
444 disable_irq(g->irq_stall);
445
446 devm_free_irq(&pdev->dev, g->irq_stall, g);
447
448#if defined(CONFIG_PCI_MSI)
449 if (g->msi_enabled) {
450 pci_disable_msi(pdev);
451 g->msi_enabled = false;
452 }
453#endif
454 gk20a_dbg(gpu_dbg_shutdown, "IRQs disabled.\n");
455
456 /*
457 * Wait for the driver to finish up all the IOCTLs it's working on
458 * before cleaning up the driver's data structures.
459 */
460 gk20a_driver_start_unload(g);
461 gk20a_dbg(gpu_dbg_shutdown, "Driver idle.\n");
462
463#ifdef CONFIG_ARCH_TEGRA_18x_SOC
464 nvgpu_clk_arb_cleanup_arbiter(g);
465#endif
466
467 gk20a_user_deinit(g->dev, &nvgpu_pci_class);
468 gk20a_dbg(gpu_dbg_shutdown, "User de-init done.\b");
469
470 debugfs_remove_recursive(platform->debugfs);
471 debugfs_remove_recursive(platform->debugfs_alias);
472
473 gk20a_remove_sysfs(g->dev);
474
475 if (platform->remove)
476 platform->remove(g->dev);
477 gk20a_dbg(gpu_dbg_shutdown, "Platform remove done.\b");
478
479 enable_irq(g->irq_stall);
480
481 gk20a_get_platform(&pdev->dev)->g = NULL;
482 gk20a_put(g);
483}
484
485static struct pci_driver nvgpu_pci_driver = {
486 .name = "nvgpu",
487 .id_table = nvgpu_pci_table,
488 .probe = nvgpu_pci_probe,
489 .remove = nvgpu_pci_remove,
490#ifdef CONFIG_PM
491 .driver.pm = &nvgpu_pci_pm_ops,
492#endif
493};
494
495int __init nvgpu_pci_init(void)
496{
497 int ret;
498
499 ret = class_register(&nvgpu_pci_class);
500 if (ret)
501 return ret;
502
503 return pci_register_driver(&nvgpu_pci_driver);
504}
505
506void __exit nvgpu_pci_exit(void)
507{
508 pci_unregister_driver(&nvgpu_pci_driver);
509 class_unregister(&nvgpu_pci_class);
510}
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