diff options
author | Konsta Holtta <kholtta@nvidia.com> | 2018-09-21 08:28:15 -0400 |
---|---|---|
committer | Konsta Holtta <kholtta@nvidia.com> | 2018-09-21 10:55:39 -0400 |
commit | ce5228e09411f9c54e96cfb0f7e9c857fd9b480d (patch) | |
tree | 26bbc69aa41fc1cb78746540cbf395f6a9cdda12 /drivers/gpu/nvgpu/os | |
parent | 84097d54f3b9ff242c4c3fb3c0a95353e8513b33 (diff) |
Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"
This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb.
Bug 2400508
Jira VQRM-4806
Bug 200447406
Bug 2331747
Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837223
Diffstat (limited to 'drivers/gpu/nvgpu/os')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 50 |
1 files changed, 41 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index fa33b6e0..953b7168 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -154,6 +154,10 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s); | |||
154 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | 154 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, |
155 | struct file *filp, bool is_profiler); | 155 | struct file *filp, bool is_profiler); |
156 | 156 | ||
157 | static int nvgpu_set_sm_exception_type_mask_locked( | ||
158 | struct dbg_session_gk20a *dbg_s, | ||
159 | u32 exception_mask); | ||
160 | |||
157 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) | 161 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) |
158 | { | 162 | { |
159 | unsigned int mask = 0; | 163 | unsigned int mask = 0; |
@@ -1804,13 +1808,44 @@ out: | |||
1804 | return err; | 1808 | return err; |
1805 | } | 1809 | } |
1806 | 1810 | ||
1807 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *dbg_s, | 1811 | static int nvgpu_set_sm_exception_type_mask_locked( |
1812 | struct dbg_session_gk20a *dbg_s, | ||
1813 | u32 exception_mask) | ||
1814 | { | ||
1815 | struct gk20a *g = dbg_s->g; | ||
1816 | int err = 0; | ||
1817 | struct channel_gk20a *ch = NULL; | ||
1818 | |||
1819 | /* | ||
1820 | * Obtain the fisrt channel from the channel list in | ||
1821 | * dbg_session, find the context associated with channel | ||
1822 | * and set the sm_mask_type to that context | ||
1823 | */ | ||
1824 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
1825 | if (ch != NULL) { | ||
1826 | struct tsg_gk20a *tsg; | ||
1827 | |||
1828 | tsg = tsg_gk20a_from_ch(ch); | ||
1829 | if (tsg != NULL) { | ||
1830 | tsg->sm_exception_mask_type = exception_mask; | ||
1831 | goto type_mask_end; | ||
1832 | } | ||
1833 | } | ||
1834 | |||
1835 | nvgpu_log_fn(g, "unable to find the TSG\n"); | ||
1836 | err = -EINVAL; | ||
1837 | |||
1838 | type_mask_end: | ||
1839 | return err; | ||
1840 | } | ||
1841 | |||
1842 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | ||
1843 | struct dbg_session_gk20a *dbg_s, | ||
1808 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) | 1844 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) |
1809 | { | 1845 | { |
1810 | int err = 0; | 1846 | int err = 0; |
1811 | struct gk20a *g = dbg_s->g; | 1847 | struct gk20a *g = dbg_s->g; |
1812 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | 1848 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; |
1813 | struct channel_gk20a *ch = NULL; | ||
1814 | 1849 | ||
1815 | switch (args->exception_type_mask) { | 1850 | switch (args->exception_type_mask) { |
1816 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | 1851 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: |
@@ -1831,13 +1866,10 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *db | |||
1831 | return err; | 1866 | return err; |
1832 | } | 1867 | } |
1833 | 1868 | ||
1834 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | 1869 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
1835 | if (ch != NULL) { | 1870 | err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, |
1836 | err = g->ops.fifo.set_sm_exception_type_mask(ch, | 1871 | sm_exception_mask_type); |
1837 | sm_exception_mask_type); | 1872 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1838 | } else { | ||
1839 | err = -EINVAL; | ||
1840 | } | ||
1841 | 1873 | ||
1842 | return err; | 1874 | return err; |
1843 | } | 1875 | } |