nvgpu: gpu: Support multiple tpc-pg masks.

- TPC powergating should be done before
  calling gk20a_enable_gr_hw.
  gk20a_enable_gr_hw() issues a GR engine reset.

  Without this fix, enabling 1 TPC from each PES
  causes ctxsw timeout error while running GFX Benchmark.

- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
    TPC Config - TPC-MASK
  4 TPC configuration - 0x0
  3 TPC configuration - 0x1/0x2/0x4/0x8
  2 TPC configuration - 0x5/0x9/0x6/0xa

- We should not write to gr_fe_tpc_pesmask_r()
  as part of TPC-PG sequence. This register is for
  debug purpose only.

Bug 200442360

Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 22 insertions, 5 deletions

diff --git a/drivers/gpu/nvgpu/os/linux/driver_common.c b/drivers/gpu/nvgpu/os/linux/driver_common.c
index 9ff32d68..539f0559 100644
--- a/drivers/gpu/nvgpu/os/linux/driver_common.c
+++ b/drivers/gpu/nvgpu/os/linux/driver_common.c
@@ -135,6 +135,7 @@ static void nvgpu_init_timeslice(struct gk20a *g)
 static void nvgpu_init_pm_vars(struct gk20a *g)
 {
         struct gk20a_platform *platform = dev_get_drvdata(dev_from_gk20a(g));
+        u32 i = 0;
 
         /*
          * Set up initial power settings. For non-slicon platforms, disable
@@ -172,7 +173,10 @@ static void nvgpu_init_pm_vars(struct gk20a *g)
         g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g));
         __nvgpu_set_enabled(g, NVGPU_CAN_RAILGATE, platform->can_railgate_init);
         g->can_tpc_powergate = platform->can_tpc_powergate;
-        g->valid_tpc_mask = platform->valid_tpc_mask;
+
+        for (i = 0; i < MAX_TPC_PG_CONFIGS; i++)
+                g->valid_tpc_mask[i] = platform->valid_tpc_mask[i];
+
         g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init;
         /* if default delay is not set, set default delay to 500msec */
         if (platform->railgate_delay_init)
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h
index 3a0227a1..a19d0a7c 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gk20a.h
+++ b/drivers/gpu/nvgpu/os/linux/platform_gk20a.h
@@ -74,7 +74,7 @@ struct gk20a_platform {
         struct reset_control *reset_control;
 #endif
         /* valid TPC-MASK */
-        u32 valid_tpc_mask;
+        u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];
 
         /* Delay before rail gated */
         int railgate_delay_init;
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
index 41cba0f0..dafa05e5 100644
--- a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
+++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
@@ -233,7 +233,9 @@ struct gk20a_platform gv11b_tegra_platform = {
         .can_railgate_init      = true,
 
         .can_tpc_powergate      = true,
-        .valid_tpc_mask         = 0xc,
+        .valid_tpc_mask[0]      = 0x0,
+        .valid_tpc_mask[1]      = 0x1,
+        .valid_tpc_mask[2]      = 0x5,
 
         .can_slcg               = true,
         .can_blcg               = true,
diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c
index 9e48e45d..1ffb6539 100644
--- a/drivers/gpu/nvgpu/os/linux/sysfs.c
+++ b/drivers/gpu/nvgpu/os/linux/sysfs.c
@@ -865,6 +865,18 @@ static ssize_t tpc_pg_mask_read(struct device *dev,
         return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask);
 }
 
+static bool is_tpc_mask_valid(struct gk20a *g, u32 tpc_mask)
+{
+        u32 i;
+        bool valid = false;
+
+        for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
+                if (tpc_mask == g->valid_tpc_mask[i])
+                        valid = true;
+        }
+        return valid;
+}
+
 static ssize_t tpc_pg_mask_store(struct device *dev,
         struct device_attribute *attr, const char *buf, size_t count)
 {
@@ -896,10 +908,9 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
                 return -ENODEV;
         }
 
-        if (val == TPC_MASK_FOR_ALL_ACTIVE_TPCs || val == g->valid_tpc_mask) {
+        if (is_tpc_mask_valid(g, (u32)val)) {
                 g->tpc_pg_mask = val;
         } else {
-
                 nvgpu_err(g, "TPC-PG mask is invalid");
                 nvgpu_mutex_release(&g->tpc_pg_lock);
                 return -EINVAL;