diff options
author | Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com> | 2018-12-13 06:59:20 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-06-30 13:07:26 -0400 |
commit | f56874aec2ec61f2c341b813cc76de5acc51ea12 (patch) | |
tree | efd3d6a3921c930a76bf0cb7011ca6b9809ed5f3 /drivers/gpu/nvgpu/os/linux | |
parent | bbef4c6927a13a24821c43cb2b6af72f859f7deb (diff) |
gpu: nvgpu: add speculative barrier
Data can be speculativerly stored and
code flow can be hijacked.
To mitigate this problem insert a
speculation barrier.
Bug 200447167
Change-Id: Ia865ff2add8b30de49aa970715625b13e8f71c08
Signed-off-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972221
(cherry picked from commit f0762ed4831b3fe6cc953a4a4ec26c2537dcb69f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/1996052
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/dmabuf_vidmem.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_as.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_channel.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_tsg.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/sched.c | 1 |
7 files changed, 32 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/dmabuf_vidmem.c b/drivers/gpu/nvgpu/os/linux/dmabuf_vidmem.c index 8b38a9e1..bada5dc7 100644 --- a/drivers/gpu/nvgpu/os/linux/dmabuf_vidmem.c +++ b/drivers/gpu/nvgpu/os/linux/dmabuf_vidmem.c | |||
@@ -244,6 +244,7 @@ int nvgpu_vidmem_buf_access_memory(struct gk20a *g, struct dma_buf *dmabuf, | |||
244 | vidmem_buf = dmabuf->priv; | 244 | vidmem_buf = dmabuf->priv; |
245 | mem = vidmem_buf->mem; | 245 | mem = vidmem_buf->mem; |
246 | 246 | ||
247 | nvgpu_speculation_barrier(); | ||
247 | switch (cmd) { | 248 | switch (cmd) { |
248 | case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ: | 249 | case NVGPU_DBG_GPU_IOCTL_ACCESS_FB_MEMORY_CMD_READ: |
249 | nvgpu_mem_rd_n(g, mem, offset, buffer, size); | 250 | nvgpu_mem_rd_n(g, mem, offset, buffer, size); |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_as.c b/drivers/gpu/nvgpu/os/linux/ioctl_as.c index 3fa8aa2c..f0cec178 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_as.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_as.c | |||
@@ -170,6 +170,7 @@ static int gk20a_as_ioctl_map_buffer_batch( | |||
170 | nvgpu_vm_unmap(as_share->vm, unmap_args.offset, &batch); | 170 | nvgpu_vm_unmap(as_share->vm, unmap_args.offset, &batch); |
171 | } | 171 | } |
172 | 172 | ||
173 | nvgpu_speculation_barrier(); | ||
173 | if (err) { | 174 | if (err) { |
174 | nvgpu_vm_mapping_batch_finish(as_share->vm, &batch); | 175 | nvgpu_vm_mapping_batch_finish(as_share->vm, &batch); |
175 | 176 | ||
@@ -355,6 +356,7 @@ long gk20a_as_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | |||
355 | if (err) | 356 | if (err) |
356 | return err; | 357 | return err; |
357 | 358 | ||
359 | nvgpu_speculation_barrier(); | ||
358 | switch (cmd) { | 360 | switch (cmd) { |
359 | case NVGPU_AS_IOCTL_BIND_CHANNEL: | 361 | case NVGPU_AS_IOCTL_BIND_CHANNEL: |
360 | trace_gk20a_as_ioctl_bind_channel(g->name); | 362 | trace_gk20a_as_ioctl_bind_channel(g->name); |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c index 22177171..3c844491 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c | |||
@@ -290,6 +290,7 @@ static int gk20a_channel_cycle_stats_snapshot(struct channel_gk20a *ch, | |||
290 | if (!args->dmabuf_fd) | 290 | if (!args->dmabuf_fd) |
291 | return -EINVAL; | 291 | return -EINVAL; |
292 | 292 | ||
293 | nvgpu_speculation_barrier(); | ||
293 | /* handle the command (most frequent cases first) */ | 294 | /* handle the command (most frequent cases first) */ |
294 | switch (args->cmd) { | 295 | switch (args->cmd) { |
295 | case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH: | 296 | case NVGPU_IOCTL_CHANNEL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH: |
@@ -874,6 +875,7 @@ clean_up: | |||
874 | */ | 875 | */ |
875 | u32 nvgpu_get_common_runlist_level(u32 level) | 876 | u32 nvgpu_get_common_runlist_level(u32 level) |
876 | { | 877 | { |
878 | nvgpu_speculation_barrier(); | ||
877 | switch (level) { | 879 | switch (level) { |
878 | case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: | 880 | case NVGPU_RUNLIST_INTERLEAVE_LEVEL_LOW: |
879 | return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW; | 881 | return NVGPU_FIFO_RUNLIST_INTERLEAVE_LEVEL_LOW; |
@@ -982,6 +984,7 @@ u32 nvgpu_get_ioctl_compute_preempt_mode(u32 compute_preempt_mode) | |||
982 | */ | 984 | */ |
983 | static u32 nvgpu_get_common_graphics_preempt_mode(u32 graphics_preempt_mode) | 985 | static u32 nvgpu_get_common_graphics_preempt_mode(u32 graphics_preempt_mode) |
984 | { | 986 | { |
987 | nvgpu_speculation_barrier(); | ||
985 | switch (graphics_preempt_mode) { | 988 | switch (graphics_preempt_mode) { |
986 | case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI: | 989 | case NVGPU_GRAPHICS_PREEMPTION_MODE_WFI: |
987 | return NVGPU_PREEMPTION_MODE_GRAPHICS_WFI; | 990 | return NVGPU_PREEMPTION_MODE_GRAPHICS_WFI; |
@@ -998,6 +1001,7 @@ static u32 nvgpu_get_common_graphics_preempt_mode(u32 graphics_preempt_mode) | |||
998 | */ | 1001 | */ |
999 | static u32 nvgpu_get_common_compute_preempt_mode(u32 compute_preempt_mode) | 1002 | static u32 nvgpu_get_common_compute_preempt_mode(u32 compute_preempt_mode) |
1000 | { | 1003 | { |
1004 | nvgpu_speculation_barrier(); | ||
1001 | switch (compute_preempt_mode) { | 1005 | switch (compute_preempt_mode) { |
1002 | case NVGPU_COMPUTE_PREEMPTION_MODE_WFI: | 1006 | case NVGPU_COMPUTE_PREEMPTION_MODE_WFI: |
1003 | return NVGPU_PREEMPTION_MODE_COMPUTE_WFI; | 1007 | return NVGPU_PREEMPTION_MODE_COMPUTE_WFI; |
@@ -1121,6 +1125,7 @@ long gk20a_channel_ioctl(struct file *filp, | |||
1121 | /* this ioctl call keeps a ref to the file which keeps a ref to the | 1125 | /* this ioctl call keeps a ref to the file which keeps a ref to the |
1122 | * channel */ | 1126 | * channel */ |
1123 | 1127 | ||
1128 | nvgpu_speculation_barrier(); | ||
1124 | switch (cmd) { | 1129 | switch (cmd) { |
1125 | case NVGPU_IOCTL_CHANNEL_OPEN: | 1130 | case NVGPU_IOCTL_CHANNEL_OPEN: |
1126 | err = gk20a_channel_open_ioctl(ch->g, | 1131 | err = gk20a_channel_open_ioctl(ch->g, |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index 271c5d92..954b08b5 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | |||
@@ -366,6 +366,7 @@ gk20a_ctrl_ioctl_gpu_characteristics( | |||
366 | if (request->gpu_characteristics_buf_size > 0) { | 366 | if (request->gpu_characteristics_buf_size > 0) { |
367 | size_t write_size = sizeof(gpu); | 367 | size_t write_size = sizeof(gpu); |
368 | 368 | ||
369 | nvgpu_speculation_barrier(); | ||
369 | if (write_size > request->gpu_characteristics_buf_size) | 370 | if (write_size > request->gpu_characteristics_buf_size) |
370 | write_size = request->gpu_characteristics_buf_size; | 371 | write_size = request->gpu_characteristics_buf_size; |
371 | 372 | ||
@@ -556,6 +557,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g, | |||
556 | if (args->mask_buf_size > 0) { | 557 | if (args->mask_buf_size > 0) { |
557 | size_t write_size = gpc_tpc_mask_size; | 558 | size_t write_size = gpc_tpc_mask_size; |
558 | 559 | ||
560 | nvgpu_speculation_barrier(); | ||
559 | if (write_size > args->mask_buf_size) | 561 | if (write_size > args->mask_buf_size) |
560 | write_size = args->mask_buf_size; | 562 | write_size = args->mask_buf_size; |
561 | 563 | ||
@@ -580,6 +582,7 @@ static int gk20a_ctrl_get_fbp_l2_masks( | |||
580 | if (args->mask_buf_size > 0) { | 582 | if (args->mask_buf_size > 0) { |
581 | size_t write_size = fbp_l2_mask_size; | 583 | size_t write_size = fbp_l2_mask_size; |
582 | 584 | ||
585 | nvgpu_speculation_barrier(); | ||
583 | if (write_size > args->mask_buf_size) | 586 | if (write_size > args->mask_buf_size) |
584 | write_size = args->mask_buf_size; | 587 | write_size = args->mask_buf_size; |
585 | 588 | ||
@@ -1245,6 +1248,7 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1245 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain))) | 1248 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain))) |
1246 | return -EINVAL; | 1249 | return -EINVAL; |
1247 | } | 1250 | } |
1251 | nvgpu_speculation_barrier(); | ||
1248 | 1252 | ||
1249 | entry = (struct nvgpu_gpu_clk_info __user *) | 1253 | entry = (struct nvgpu_gpu_clk_info __user *) |
1250 | (uintptr_t)args->clk_info_entries; | 1254 | (uintptr_t)args->clk_info_entries; |
@@ -1264,6 +1268,7 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1264 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), freq_mhz); | 1268 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), freq_mhz); |
1265 | } | 1269 | } |
1266 | 1270 | ||
1271 | nvgpu_speculation_barrier(); | ||
1267 | ret = nvgpu_clk_arb_commit_request_fd(g, session, fd); | 1272 | ret = nvgpu_clk_arb_commit_request_fd(g, session, fd); |
1268 | if (ret < 0) | 1273 | if (ret < 0) |
1269 | return ret; | 1274 | return ret; |
@@ -1333,6 +1338,7 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1333 | clk_info.clk_type = args->clk_type; | 1338 | clk_info.clk_type = args->clk_type; |
1334 | } | 1339 | } |
1335 | 1340 | ||
1341 | nvgpu_speculation_barrier(); | ||
1336 | switch (clk_info.clk_type) { | 1342 | switch (clk_info.clk_type) { |
1337 | case NVGPU_GPU_CLK_TYPE_TARGET: | 1343 | case NVGPU_GPU_CLK_TYPE_TARGET: |
1338 | err = nvgpu_clk_arb_get_session_target_mhz(session, | 1344 | err = nvgpu_clk_arb_get_session_target_mhz(session, |
@@ -1366,6 +1372,7 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1366 | return -EFAULT; | 1372 | return -EFAULT; |
1367 | } | 1373 | } |
1368 | 1374 | ||
1375 | nvgpu_speculation_barrier(); | ||
1369 | args->num_entries = num_entries; | 1376 | args->num_entries = num_entries; |
1370 | 1377 | ||
1371 | return 0; | 1378 | return 0; |
@@ -1403,6 +1410,7 @@ static int nvgpu_gpu_get_voltage(struct gk20a *g, | |||
1403 | if (err) | 1410 | if (err) |
1404 | return err; | 1411 | return err; |
1405 | 1412 | ||
1413 | nvgpu_speculation_barrier(); | ||
1406 | switch (args->which) { | 1414 | switch (args->which) { |
1407 | case NVGPU_GPU_VOLTAGE_CORE: | 1415 | case NVGPU_GPU_VOLTAGE_CORE: |
1408 | err = volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &args->voltage); | 1416 | err = volt_get_voltage(g, CTRL_VOLT_DOMAIN_LOGIC, &args->voltage); |
@@ -1625,6 +1633,7 @@ static int nvgpu_gpu_set_deterministic_opts(struct gk20a *g, | |||
1625 | break; | 1633 | break; |
1626 | } | 1634 | } |
1627 | 1635 | ||
1636 | nvgpu_speculation_barrier(); | ||
1628 | nvgpu_rwsem_up_read(&g->deterministic_busy); | 1637 | nvgpu_rwsem_up_read(&g->deterministic_busy); |
1629 | 1638 | ||
1630 | out: | 1639 | out: |
@@ -1668,6 +1677,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1668 | gk20a_idle(g); | 1677 | gk20a_idle(g); |
1669 | } | 1678 | } |
1670 | 1679 | ||
1680 | nvgpu_speculation_barrier(); | ||
1671 | switch (cmd) { | 1681 | switch (cmd) { |
1672 | case NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE: | 1682 | case NVGPU_GPU_IOCTL_ZCULL_GET_CTX_SIZE: |
1673 | get_ctx_size_args = (struct nvgpu_gpu_zcull_get_ctx_size_args *)buf; | 1683 | get_ctx_size_args = (struct nvgpu_gpu_zcull_get_ctx_size_args *)buf; |
@@ -1713,6 +1723,7 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
1713 | zbc_val->format = set_table_args->format; | 1723 | zbc_val->format = set_table_args->format; |
1714 | zbc_val->type = set_table_args->type; | 1724 | zbc_val->type = set_table_args->type; |
1715 | 1725 | ||
1726 | nvgpu_speculation_barrier(); | ||
1716 | switch (zbc_val->type) { | 1727 | switch (zbc_val->type) { |
1717 | case GK20A_ZBC_TYPE_COLOR: | 1728 | case GK20A_ZBC_TYPE_COLOR: |
1718 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { | 1729 | for (i = 0; i < GK20A_ZBC_COLOR_VALUE_SIZE; i++) { |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index dc732dc5..0c9b10b5 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -314,6 +314,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state( | |||
314 | if (args->sm_error_state_record_size > 0) { | 314 | if (args->sm_error_state_record_size > 0) { |
315 | size_t write_size = sizeof(*sm_error_state); | 315 | size_t write_size = sizeof(*sm_error_state); |
316 | 316 | ||
317 | nvgpu_speculation_barrier(); | ||
317 | if (write_size > args->sm_error_state_record_size) | 318 | if (write_size > args->sm_error_state_record_size) |
318 | write_size = args->sm_error_state_record_size; | 319 | write_size = args->sm_error_state_record_size; |
319 | 320 | ||
@@ -361,6 +362,7 @@ static int nvgpu_dbg_timeout_enable(struct dbg_session_gk20a *dbg_s, | |||
361 | nvgpu_log(g, gpu_dbg_gpu_dbg, "Timeouts mode requested : %d", | 362 | nvgpu_log(g, gpu_dbg_gpu_dbg, "Timeouts mode requested : %d", |
362 | timeout_mode); | 363 | timeout_mode); |
363 | 364 | ||
365 | nvgpu_speculation_barrier(); | ||
364 | switch (timeout_mode) { | 366 | switch (timeout_mode) { |
365 | case NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE: | 367 | case NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE: |
366 | if (dbg_s->is_timeout_disabled == true) | 368 | if (dbg_s->is_timeout_disabled == true) |
@@ -917,6 +919,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
917 | ops_offset += num_ops; | 919 | ops_offset += num_ops; |
918 | } | 920 | } |
919 | 921 | ||
922 | nvgpu_speculation_barrier(); | ||
920 | nvgpu_kfree(g, linux_fragment); | 923 | nvgpu_kfree(g, linux_fragment); |
921 | 924 | ||
922 | /* enable powergate, if previously disabled */ | 925 | /* enable powergate, if previously disabled */ |
@@ -1007,6 +1010,7 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
1007 | 1010 | ||
1008 | static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode) | 1011 | static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode) |
1009 | { | 1012 | { |
1013 | nvgpu_speculation_barrier(); | ||
1010 | switch (mode){ | 1014 | switch (mode){ |
1011 | case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW: | 1015 | case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW: |
1012 | return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW; | 1016 | return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW; |
@@ -1153,6 +1157,7 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | |||
1153 | goto clean_up; | 1157 | goto clean_up; |
1154 | } | 1158 | } |
1155 | 1159 | ||
1160 | nvgpu_speculation_barrier(); | ||
1156 | switch (action) { | 1161 | switch (action) { |
1157 | case NVGPU_DBG_GPU_SUSPEND_ALL_SMS: | 1162 | case NVGPU_DBG_GPU_SUSPEND_ALL_SMS: |
1158 | gr_gk20a_suspend_context(ch); | 1163 | gr_gk20a_suspend_context(ch); |
@@ -1366,6 +1371,7 @@ static int gk20a_dbg_gpu_events_ctrl(struct dbg_session_gk20a *dbg_s, | |||
1366 | return -EINVAL; | 1371 | return -EINVAL; |
1367 | } | 1372 | } |
1368 | 1373 | ||
1374 | nvgpu_speculation_barrier(); | ||
1369 | switch (args->cmd) { | 1375 | switch (args->cmd) { |
1370 | case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE: | 1376 | case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE: |
1371 | gk20a_dbg_gpu_events_enable(dbg_s); | 1377 | gk20a_dbg_gpu_events_enable(dbg_s); |
@@ -1536,6 +1542,7 @@ nvgpu_dbg_gpu_ioctl_suspend_resume_contexts(struct dbg_session_gk20a *dbg_s, | |||
1536 | if (err) | 1542 | if (err) |
1537 | return err; | 1543 | return err; |
1538 | 1544 | ||
1545 | nvgpu_speculation_barrier(); | ||
1539 | switch (args->action) { | 1546 | switch (args->action) { |
1540 | case NVGPU_DBG_GPU_SUSPEND_ALL_CONTEXTS: | 1547 | case NVGPU_DBG_GPU_SUSPEND_ALL_CONTEXTS: |
1541 | err = g->ops.gr.suspend_contexts(g, dbg_s, | 1548 | err = g->ops.gr.suspend_contexts(g, dbg_s, |
@@ -1627,6 +1634,7 @@ static int nvgpu_dbg_gpu_ioctl_access_fb_memory(struct dbg_session_gk20a *dbg_s, | |||
1627 | size -= access_size; | 1634 | size -= access_size; |
1628 | offset += access_size; | 1635 | offset += access_size; |
1629 | } | 1636 | } |
1637 | nvgpu_speculation_barrier(); | ||
1630 | 1638 | ||
1631 | fail_idle: | 1639 | fail_idle: |
1632 | gk20a_idle(g); | 1640 | gk20a_idle(g); |
@@ -1899,6 +1907,7 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | |||
1899 | struct gk20a *g = dbg_s->g; | 1907 | struct gk20a *g = dbg_s->g; |
1900 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | 1908 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; |
1901 | 1909 | ||
1910 | nvgpu_speculation_barrier(); | ||
1902 | switch (args->exception_type_mask) { | 1911 | switch (args->exception_type_mask) { |
1903 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | 1912 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: |
1904 | sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; | 1913 | sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; |
@@ -1970,6 +1979,7 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
1970 | /* protect from threaded user space calls */ | 1979 | /* protect from threaded user space calls */ |
1971 | nvgpu_mutex_acquire(&dbg_s->ioctl_lock); | 1980 | nvgpu_mutex_acquire(&dbg_s->ioctl_lock); |
1972 | 1981 | ||
1982 | nvgpu_speculation_barrier(); | ||
1973 | switch (cmd) { | 1983 | switch (cmd) { |
1974 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: | 1984 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: |
1975 | err = dbg_bind_channel_gk20a(dbg_s, | 1985 | err = dbg_bind_channel_gk20a(dbg_s, |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c index a26559f5..2f8cb3ae 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_tsg.c | |||
@@ -361,6 +361,7 @@ static int gk20a_tsg_event_id_ctrl(struct gk20a *g, struct tsg_gk20a *tsg, | |||
361 | if (args->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) | 361 | if (args->event_id >= NVGPU_IOCTL_CHANNEL_EVENT_ID_MAX) |
362 | return -EINVAL; | 362 | return -EINVAL; |
363 | 363 | ||
364 | nvgpu_speculation_barrier(); | ||
364 | switch (args->cmd) { | 365 | switch (args->cmd) { |
365 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE: | 366 | case NVGPU_IOCTL_CHANNEL_EVENT_ID_CMD_ENABLE: |
366 | err = gk20a_tsg_event_id_enable(tsg, args->event_id, &fd); | 367 | err = gk20a_tsg_event_id_enable(tsg, args->event_id, &fd); |
@@ -572,6 +573,7 @@ static int gk20a_tsg_ioctl_read_single_sm_error_state(struct gk20a *g, | |||
572 | if (args->record_size > 0) { | 573 | if (args->record_size > 0) { |
573 | size_t write_size = sizeof(*sm_error_state); | 574 | size_t write_size = sizeof(*sm_error_state); |
574 | 575 | ||
576 | nvgpu_speculation_barrier(); | ||
575 | if (write_size > args->record_size) | 577 | if (write_size > args->record_size) |
576 | write_size = args->record_size; | 578 | write_size = args->record_size; |
577 | 579 | ||
diff --git a/drivers/gpu/nvgpu/os/linux/sched.c b/drivers/gpu/nvgpu/os/linux/sched.c index 15cbf1ec..30c58a19 100644 --- a/drivers/gpu/nvgpu/os/linux/sched.c +++ b/drivers/gpu/nvgpu/os/linux/sched.c | |||
@@ -447,6 +447,7 @@ long gk20a_sched_dev_ioctl(struct file *filp, unsigned int cmd, | |||
447 | return -EFAULT; | 447 | return -EFAULT; |
448 | } | 448 | } |
449 | 449 | ||
450 | nvgpu_speculation_barrier(); | ||
450 | switch (cmd) { | 451 | switch (cmd) { |
451 | case NVGPU_SCHED_IOCTL_GET_TSGS: | 452 | case NVGPU_SCHED_IOCTL_GET_TSGS: |
452 | err = gk20a_sched_dev_ioctl_get_tsgs(g, | 453 | err = gk20a_sched_dev_ioctl_get_tsgs(g, |