diff options
author | Vinod G <vinodg@nvidia.com> | 2018-08-29 15:32:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-31 21:57:23 -0400 |
commit | f187e0bf442c3b0a08c46b21196f06a18c8220a0 (patch) | |
tree | 48820c076f6ab4a2bad6ab6053d26293c99326c3 /drivers/gpu/nvgpu/os/linux | |
parent | b25d5d86caa049201ddcea77cf1a733a85090698 (diff) |
gpu: nvgpu: Move SM_MASK_TYPE setting to TSG level
Moved the SM_MASK_TYPE variable from GR to
TSG struct. SM error registers are context based.
In dbg_session IOCTL to SET_SM_MASK_TYPE, kernel
code iterate the TSG associated with first channel
and set the mask_type to that context.
Bug 200412641
Change-Id: Ic91944037ad2447f403b4803d5266ae6250ba4c9
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809322
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 71 |
1 files changed, 39 insertions, 32 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 4ac4fb62..3931ab12 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -223,10 +223,6 @@ int gk20a_dbg_gpu_dev_release(struct inode *inode, struct file *filp) | |||
223 | nvgpu_kfree(g, prof_obj); | 223 | nvgpu_kfree(g, prof_obj); |
224 | } | 224 | } |
225 | } | 225 | } |
226 | |||
227 | nvgpu_set_sm_exception_type_mask_locked(dbg_s, | ||
228 | NVGPU_SM_EXCEPTION_TYPE_MASK_NONE); | ||
229 | |||
230 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 226 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
231 | 227 | ||
232 | nvgpu_mutex_destroy(&dbg_s->ch_list_lock); | 228 | nvgpu_mutex_destroy(&dbg_s->ch_list_lock); |
@@ -499,7 +495,6 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | |||
499 | dbg_s->is_profiler = is_profiler; | 495 | dbg_s->is_profiler = is_profiler; |
500 | dbg_s->is_pg_disabled = false; | 496 | dbg_s->is_pg_disabled = false; |
501 | dbg_s->is_timeout_disabled = false; | 497 | dbg_s->is_timeout_disabled = false; |
502 | dbg_s->is_sm_exception_type_mask_set = false; | ||
503 | 498 | ||
504 | nvgpu_cond_init(&dbg_s->dbg_events.wait_queue); | 499 | nvgpu_cond_init(&dbg_s->dbg_events.wait_queue); |
505 | nvgpu_init_list_node(&dbg_s->ch_list); | 500 | nvgpu_init_list_node(&dbg_s->ch_list); |
@@ -512,9 +507,6 @@ static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | |||
512 | dbg_s->dbg_events.events_enabled = false; | 507 | dbg_s->dbg_events.events_enabled = false; |
513 | dbg_s->dbg_events.num_pending_events = 0; | 508 | dbg_s->dbg_events.num_pending_events = 0; |
514 | 509 | ||
515 | nvgpu_set_sm_exception_type_mask_locked(dbg_s, | ||
516 | NVGPU_SM_EXCEPTION_TYPE_MASK_NONE); | ||
517 | |||
518 | return 0; | 510 | return 0; |
519 | 511 | ||
520 | err_destroy_lock: | 512 | err_destroy_lock: |
@@ -1887,34 +1879,29 @@ static int nvgpu_set_sm_exception_type_mask_locked( | |||
1887 | u32 exception_mask) | 1879 | u32 exception_mask) |
1888 | { | 1880 | { |
1889 | struct gk20a *g = dbg_s->g; | 1881 | struct gk20a *g = dbg_s->g; |
1890 | struct gr_gk20a *gr = &g->gr; | ||
1891 | int err = 0; | 1882 | int err = 0; |
1883 | struct channel_gk20a *ch = NULL; | ||
1892 | 1884 | ||
1893 | switch (exception_mask) { | 1885 | /* |
1894 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | 1886 | * Obtain the fisrt channel from the channel list in |
1895 | gr->sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; | 1887 | * dbg_session, find the context associated with channel |
1896 | if (dbg_s->is_sm_exception_type_mask_set == false) { | 1888 | * and set the sm_mask_type to that context |
1897 | gr->sm_exception_mask_refcount++; | 1889 | */ |
1898 | dbg_s->is_sm_exception_type_mask_set = true; | 1890 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); |
1899 | } | 1891 | if (ch != NULL) { |
1900 | break; | 1892 | struct tsg_gk20a *tsg; |
1901 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_NONE: | 1893 | |
1902 | if (dbg_s->is_sm_exception_type_mask_set) { | 1894 | tsg = tsg_gk20a_from_ch(ch); |
1903 | gr->sm_exception_mask_refcount--; | 1895 | if (tsg != NULL) { |
1904 | dbg_s->is_sm_exception_type_mask_set = false; | 1896 | tsg->sm_exception_mask_type = exception_mask; |
1897 | goto type_mask_end; | ||
1905 | } | 1898 | } |
1906 | if (gr->sm_exception_mask_refcount == 0) | ||
1907 | gr->sm_exception_mask_type = | ||
1908 | NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | ||
1909 | break; | ||
1910 | default: | ||
1911 | nvgpu_err(g, | ||
1912 | "unrecognized dbg sm exception type mask: 0x%x", | ||
1913 | exception_mask); | ||
1914 | err = -EINVAL; | ||
1915 | break; | ||
1916 | } | 1899 | } |
1917 | 1900 | ||
1901 | nvgpu_log_fn(g, "unable to find the TSG\n"); | ||
1902 | err = -EINVAL; | ||
1903 | |||
1904 | type_mask_end: | ||
1918 | return err; | 1905 | return err; |
1919 | } | 1906 | } |
1920 | 1907 | ||
@@ -1924,10 +1911,30 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | |||
1924 | { | 1911 | { |
1925 | int err = 0; | 1912 | int err = 0; |
1926 | struct gk20a *g = dbg_s->g; | 1913 | struct gk20a *g = dbg_s->g; |
1914 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | ||
1915 | |||
1916 | switch (args->exception_type_mask) { | ||
1917 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | ||
1918 | sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; | ||
1919 | break; | ||
1920 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_NONE: | ||
1921 | sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | ||
1922 | break; | ||
1923 | default: | ||
1924 | nvgpu_err(g, | ||
1925 | "unrecognized dbg sm exception type mask: 0x%x", | ||
1926 | args->exception_type_mask); | ||
1927 | err = -EINVAL; | ||
1928 | break; | ||
1929 | } | ||
1930 | |||
1931 | if (err != 0) { | ||
1932 | return err; | ||
1933 | } | ||
1927 | 1934 | ||
1928 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 1935 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
1929 | err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, | 1936 | err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, |
1930 | args->exception_type_mask); | 1937 | sm_exception_mask_type); |
1931 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1938 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1932 | 1939 | ||
1933 | return err; | 1940 | return err; |