nvgpu: gpu: Support multiple tpc-pg masks.

- TPC powergating should be done before
  calling gk20a_enable_gr_hw.
  gk20a_enable_gr_hw() issues a GR engine reset.

  Without this fix, enabling 1 TPC from each PES
  causes ctxsw timeout error while running GFX Benchmark.

- Adds valid tpc-pg mask for 1/2/3/4 active TPC configs.
    TPC Config - TPC-MASK
  4 TPC configuration - 0x0
  3 TPC configuration - 0x1/0x2/0x4/0x8
  2 TPC configuration - 0x5/0x9/0x6/0xa

- We should not write to gr_fe_tpc_pesmask_r()
  as part of TPC-PG sequence. This register is for
  debug purpose only.

Bug 200442360

Change-Id: I6fbe1ad8fbc836ace8cbaf00ec3d21a12c73e0bd
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809772
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 13 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c
index 9e48e45d..1ffb6539 100644
--- a/drivers/gpu/nvgpu/os/linux/sysfs.c
+++ b/drivers/gpu/nvgpu/os/linux/sysfs.c
@@ -865,6 +865,18 @@ static ssize_t tpc_pg_mask_read(struct device *dev,
         return snprintf(buf, PAGE_SIZE, "%d\n", g->tpc_pg_mask);
 }
 
+static bool is_tpc_mask_valid(struct gk20a *g, u32 tpc_mask)
+{
+        u32 i;
+        bool valid = false;
+
+        for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) {
+                if (tpc_mask == g->valid_tpc_mask[i])
+                        valid = true;
+        }
+        return valid;
+}
+
 static ssize_t tpc_pg_mask_store(struct device *dev,
         struct device_attribute *attr, const char *buf, size_t count)
 {
@@ -896,10 +908,9 @@ static ssize_t tpc_pg_mask_store(struct device *dev,
                 return -ENODEV;
         }
 
-        if (val == TPC_MASK_FOR_ALL_ACTIVE_TPCs || val == g->valid_tpc_mask) {
+        if (is_tpc_mask_valid(g, (u32)val)) {
                 g->tpc_pg_mask = val;
         } else {
-
                 nvgpu_err(g, "TPC-PG mask is invalid");
                 nvgpu_mutex_release(&g->tpc_pg_lock);
                 return -EINVAL;