gpu: nvgpu: changing page_idx from int to u64

page_idx is an element of the struct nvgpu_semaphore_pool, defined in
include/nvgpu/semaphore.h file.

page_idx can not be negative so changing it from int to u64 and its
related changes in various files.

This also fixes MISRA 10.4 violations in these files.

Jira NVGPU-992

Change-Id: Ie9696dab7da9e139bc31563783b422c84144f18b
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1801632
Reviewed-by: Adeel Raza <araza@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/os/linux/sync_sema_android.c b/drivers/gpu/nvgpu/os/linux/sync_sema_android.c
index 50465d0c..59e3b7a6 100644
--- a/drivers/gpu/nvgpu/os/linux/sync_sema_android.c
+++ b/drivers/gpu/nvgpu/os/linux/sync_sema_android.c
@@ -284,7 +284,7 @@ static void gk20a_sync_pt_value_str_for_sema(struct gk20a_sync_pt *pt,
 {
         struct nvgpu_semaphore *s = pt->sema;
 
-        snprintf(str, size, "S: pool=%d [v=%u,r_v=%u]",
+        snprintf(str, size, "S: pool=%llu [v=%u,r_v=%u]",
                  s->location.pool->page_idx,
                  nvgpu_semaphore_get_value(s),
                  nvgpu_semaphore_read(s));