diff options
author | Divya Singhatwaria <dsinghatwari@nvidia.com> | 2019-07-23 01:13:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2019-08-02 15:57:24 -0400 |
commit | ae175e45edc5807131dfb1b63d3e4795e96a3f86 (patch) | |
tree | c209caf5a5804f250be83e4a68295daa64d6cfb5 /drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c | |
parent | 47f6bc0c2e85d0a8ff943b88c81108ca1bfc588e (diff) |
gpu: nvgpu: Use TPC_PG_MASK to powergate the TPC
- In GV11B, read fuse_status_opt_tpc_gpc register
to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
be set to true or false and mask will be used to write to
fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
sent from userspace is valid and can be used to power gate
the desired TPC
- can_tpc_powergate = false indicates that the mask value
sent from userspace is not valid and cannot be used to
power gate the desired TPC.
Bug 200532639
Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159219
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c index 4a94c1cd..ac1958a2 100644 --- a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c | |||
@@ -218,26 +218,29 @@ static int gv11b_tegra_suspend(struct device *dev) | |||
218 | return 0; | 218 | return 0; |
219 | } | 219 | } |
220 | 220 | ||
221 | static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_mask) | 221 | static bool is_tpc_mask_valid(struct gk20a_platform *platform, u32 tpc_pg_mask) |
222 | { | 222 | { |
223 | u32 i; | 223 | u32 i; |
224 | bool valid = false; | 224 | bool valid = false; |
225 | 225 | ||
226 | for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { | 226 | for (i = 0; i < MAX_TPC_PG_CONFIGS; i++) { |
227 | if (tpc_mask == platform->valid_tpc_mask[i]) | 227 | if (tpc_pg_mask == platform->valid_tpc_mask[i]) { |
228 | valid = true; | 228 | valid = true; |
229 | break; | ||
230 | } | ||
229 | } | 231 | } |
230 | return valid; | 232 | return valid; |
231 | } | 233 | } |
232 | 234 | ||
233 | static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_mask) | 235 | static void gv11b_tegra_set_tpc_pg_mask(struct device *dev, u32 tpc_pg_mask) |
234 | { | 236 | { |
235 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 237 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
236 | struct gk20a *g = get_gk20a(dev); | 238 | struct gk20a *g = get_gk20a(dev); |
237 | 239 | ||
238 | if (is_tpc_mask_valid(platform, tpc_mask)) { | 240 | if (is_tpc_mask_valid(platform, tpc_pg_mask)) { |
239 | g->tpc_pg_mask = tpc_mask; | 241 | g->tpc_pg_mask = tpc_pg_mask; |
240 | } | 242 | } |
243 | |||
241 | } | 244 | } |
242 | 245 | ||
243 | struct gk20a_platform gv11b_tegra_platform = { | 246 | struct gk20a_platform gv11b_tegra_platform = { |
@@ -257,9 +260,15 @@ struct gk20a_platform gv11b_tegra_platform = { | |||
257 | .can_tpc_powergate = true, | 260 | .can_tpc_powergate = true, |
258 | .valid_tpc_mask[0] = 0x0, | 261 | .valid_tpc_mask[0] = 0x0, |
259 | .valid_tpc_mask[1] = 0x1, | 262 | .valid_tpc_mask[1] = 0x1, |
260 | .valid_tpc_mask[2] = 0x5, | 263 | .valid_tpc_mask[2] = 0x2, |
261 | 264 | .valid_tpc_mask[3] = 0x4, | |
262 | .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask, | 265 | .valid_tpc_mask[4] = 0x8, |
266 | .valid_tpc_mask[5] = 0x5, | ||
267 | .valid_tpc_mask[6] = 0x6, | ||
268 | .valid_tpc_mask[7] = 0x9, | ||
269 | .valid_tpc_mask[8] = 0xa, | ||
270 | |||
271 | .set_tpc_pg_mask = gv11b_tegra_set_tpc_pg_mask, | ||
263 | 272 | ||
264 | .can_slcg = true, | 273 | .can_slcg = true, |
265 | .can_blcg = true, | 274 | .can_blcg = true, |