summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2018-04-18 15:59:00 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-06-15 20:47:31 -0400
commit2a2c16af5f9f1ccfc93a13e820d5381e5c881e92 (patch)
tree2e5d7b042270a649978e5bb540857012c85fb5b5 /drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
parent98d996f4ffb0137d119b5849cae46d7b7e5693e1 (diff)
gpu: nvgpu: Move Linux files away from common
Move all Linux source code files to drivers/gpu/nvgpu/os/linux from drivers/gpu/nvgpu/common/linux. This changes the meaning of common to be OS independent. JIRA NVGPU-598 JIRA NVGPU-601 Change-Id: Ib7f2a43d3688bb0d0b7dcc48469a6783fd988ce9 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1747714 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c')
-rw-r--r--drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c588
1 files changed, 588 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
new file mode 100644
index 00000000..d62e7932
--- /dev/null
+++ b/drivers/gpu/nvgpu/os/linux/platform_gv11b_tegra.c
@@ -0,0 +1,588 @@
1/*
2 * GV11B Tegra Platform Interface
3 *
4 * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19#include <linux/of_platform.h>
20#include <linux/debugfs.h>
21#include <linux/dma-buf.h>
22#include <linux/nvmap.h>
23#include <linux/reset.h>
24#include <linux/hashtable.h>
25#include <linux/clk.h>
26#include <linux/platform/tegra/emc_bwmgr.h>
27
28#include <nvgpu/nvhost.h>
29
30#include <uapi/linux/nvgpu.h>
31
32#include <soc/tegra/tegra_bpmp.h>
33#include <soc/tegra/tegra_powergate.h>
34
35#include "gk20a/gk20a.h"
36#include "platform_gk20a.h"
37#include "clk.h"
38#include "scale.h"
39
40#include "platform_gp10b.h"
41#include "platform_gp10b_tegra.h"
42#include "platform_ecc_sysfs.h"
43
44#include "os_linux.h"
45#include "platform_gk20a_tegra.h"
46#include "gv11b/gr_gv11b.h"
47
48static void gv11b_tegra_scale_exit(struct device *dev)
49{
50 struct gk20a_platform *platform = gk20a_get_platform(dev);
51 struct gk20a_scale_profile *profile = platform->g->scale_profile;
52
53 if (profile)
54 tegra_bwmgr_unregister(
55 (struct tegra_bwmgr_client *)profile->private_data);
56}
57
58static int gv11b_tegra_probe(struct device *dev)
59{
60 struct gk20a_platform *platform = dev_get_drvdata(dev);
61 int err;
62
63 err = nvgpu_nvhost_syncpt_init(platform->g);
64 if (err) {
65 if (err != -ENOSYS)
66 return err;
67 }
68
69 err = gk20a_tegra_init_secure_alloc(platform);
70 if (err)
71 return err;
72
73 platform->disable_bigpage = !device_is_iommuable(dev);
74
75 platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
76 = false;
77 platform->g->gr.ctx_vars.dump_ctxsw_stats_on_channel_close
78 = false;
79
80 platform->g->gr.ctx_vars.force_preemption_gfxp = false;
81 platform->g->gr.ctx_vars.force_preemption_cilp = false;
82
83 gp10b_tegra_get_clocks(dev);
84 nvgpu_linux_init_clk_support(platform->g);
85
86 return 0;
87}
88
89static int gv11b_tegra_late_probe(struct device *dev)
90{
91 return 0;
92}
93
94
95static int gv11b_tegra_remove(struct device *dev)
96{
97 struct gk20a *g = get_gk20a(dev);
98
99 if (g->ops.gr.remove_gr_sysfs)
100 g->ops.gr.remove_gr_sysfs(g);
101
102 gv11b_tegra_scale_exit(dev);
103
104#ifdef CONFIG_TEGRA_GK20A_NVHOST
105 nvgpu_free_nvhost_dev(get_gk20a(dev));
106#endif
107
108 return 0;
109}
110
111static bool gv11b_tegra_is_railgated(struct device *dev)
112{
113 bool ret = false;
114#ifdef TEGRA194_POWER_DOMAIN_GPU
115 struct gk20a *g = get_gk20a(dev);
116
117 if (tegra_bpmp_running()) {
118 nvgpu_log(g, gpu_dbg_info, "bpmp running");
119 ret = !tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU);
120
121 nvgpu_log(g, gpu_dbg_info, "railgated? %s", ret ? "yes" : "no");
122 } else {
123 nvgpu_log(g, gpu_dbg_info, "bpmp not running");
124 }
125#endif
126 return ret;
127}
128
129static int gv11b_tegra_railgate(struct device *dev)
130{
131#ifdef TEGRA194_POWER_DOMAIN_GPU
132 struct gk20a_platform *platform = gk20a_get_platform(dev);
133 struct gk20a_scale_profile *profile = platform->g->scale_profile;
134 struct gk20a *g = get_gk20a(dev);
135 int i;
136
137 /* remove emc frequency floor */
138 if (profile)
139 tegra_bwmgr_set_emc(
140 (struct tegra_bwmgr_client *)profile->private_data,
141 0, TEGRA_BWMGR_SET_EMC_FLOOR);
142
143 if (tegra_bpmp_running()) {
144 nvgpu_log(g, gpu_dbg_info, "bpmp running");
145 if (!tegra_powergate_is_powered(TEGRA194_POWER_DOMAIN_GPU)) {
146 nvgpu_log(g, gpu_dbg_info, "powergate is not powered");
147 return 0;
148 }
149 nvgpu_log(g, gpu_dbg_info, "clk_disable_unprepare");
150 for (i = 0; i < platform->num_clks; i++) {
151 if (platform->clk[i])
152 clk_disable_unprepare(platform->clk[i]);
153 }
154 nvgpu_log(g, gpu_dbg_info, "powergate_partition");
155 tegra_powergate_partition(TEGRA194_POWER_DOMAIN_GPU);
156 } else {
157 nvgpu_log(g, gpu_dbg_info, "bpmp not running");
158 }
159#endif
160 return 0;
161}
162
163static int gv11b_tegra_unrailgate(struct device *dev)
164{
165 int ret = 0;
166#ifdef TEGRA194_POWER_DOMAIN_GPU
167 struct gk20a_platform *platform = gk20a_get_platform(dev);
168 struct gk20a *g = get_gk20a(dev);
169 struct gk20a_scale_profile *profile = platform->g->scale_profile;
170 int i;
171
172 if (tegra_bpmp_running()) {
173 nvgpu_log(g, gpu_dbg_info, "bpmp running");
174 ret = tegra_unpowergate_partition(TEGRA194_POWER_DOMAIN_GPU);
175 if (ret) {
176 nvgpu_log(g, gpu_dbg_info,
177 "unpowergate partition failed");
178 return ret;
179 }
180 nvgpu_log(g, gpu_dbg_info, "clk_prepare_enable");
181 for (i = 0; i < platform->num_clks; i++) {
182 if (platform->clk[i])
183 clk_prepare_enable(platform->clk[i]);
184 }
185 } else {
186 nvgpu_log(g, gpu_dbg_info, "bpmp not running");
187 }
188
189 /* to start with set emc frequency floor to max rate*/
190 if (profile)
191 tegra_bwmgr_set_emc(
192 (struct tegra_bwmgr_client *)profile->private_data,
193 tegra_bwmgr_get_max_emc_rate(),
194 TEGRA_BWMGR_SET_EMC_FLOOR);
195#endif
196 return ret;
197}
198
199static int gv11b_tegra_suspend(struct device *dev)
200{
201 return 0;
202}
203
204struct gk20a_platform gv11b_tegra_platform = {
205 .has_syncpoints = true,
206
207 /* ptimer src frequency in hz*/
208 .ptimer_src_freq = 31250000,
209
210 .ch_wdt_timeout_ms = 5000,
211
212 .probe = gv11b_tegra_probe,
213 .late_probe = gv11b_tegra_late_probe,
214 .remove = gv11b_tegra_remove,
215 .railgate_delay_init = 500,
216 .can_railgate_init = true,
217
218 .can_slcg = true,
219 .can_blcg = true,
220 .can_elcg = true,
221 .enable_slcg = true,
222 .enable_blcg = true,
223 .enable_elcg = true,
224 .enable_perfmon = true,
225
226 /* power management configuration */
227 .enable_elpg = true,
228 .can_elpg_init = true,
229 .enable_aelpg = true,
230
231 /* power management callbacks */
232 .suspend = gv11b_tegra_suspend,
233 .railgate = gv11b_tegra_railgate,
234 .unrailgate = gv11b_tegra_unrailgate,
235 .is_railgated = gv11b_tegra_is_railgated,
236
237 .busy = gk20a_tegra_busy,
238 .idle = gk20a_tegra_idle,
239
240 .clk_round_rate = gp10b_round_clk_rate,
241 .get_clk_freqs = gp10b_clk_get_freqs,
242
243 /* frequency scaling configuration */
244 .initscale = gp10b_tegra_scale_init,
245 .prescale = gp10b_tegra_prescale,
246 .postscale = gp10b_tegra_postscale,
247 .devfreq_governor = "nvhost_podgov",
248
249 .qos_notify = gk20a_scale_qos_notify,
250
251 .dump_platform_dependencies = gk20a_tegra_debug_dump,
252
253 .soc_name = "tegra19x",
254
255 .honors_aperture = true,
256 .unified_memory = true,
257 .dma_mask = DMA_BIT_MASK(36),
258
259 .reset_assert = gp10b_tegra_reset_assert,
260 .reset_deassert = gp10b_tegra_reset_deassert,
261
262 .secure_buffer_size = 667648,
263};
264
265void gr_gv11b_create_sysfs(struct gk20a *g)
266{
267 struct device *dev = dev_from_gk20a(g);
268 int error = 0;
269
270 /* This stat creation function is called on GR init. GR can get
271 initialized multiple times but we only need to create the ECC
272 stats once. Therefore, add the following check to avoid
273 creating duplicate stat sysfs nodes. */
274 if (g->ecc.gr.sm_l1_tag_corrected_err_count.counters != NULL)
275 return;
276
277 gr_gp10b_create_sysfs(g);
278
279 error |= nvgpu_gr_ecc_stat_create(dev,
280 0,
281 "sm_l1_tag_ecc_corrected_err_count",
282 &g->ecc.gr.sm_l1_tag_corrected_err_count);
283
284 error |= nvgpu_gr_ecc_stat_create(dev,
285 0,
286 "sm_l1_tag_ecc_uncorrected_err_count",
287 &g->ecc.gr.sm_l1_tag_uncorrected_err_count);
288
289 error |= nvgpu_gr_ecc_stat_create(dev,
290 0,
291 "sm_cbu_ecc_corrected_err_count",
292 &g->ecc.gr.sm_cbu_corrected_err_count);
293
294 error |= nvgpu_gr_ecc_stat_create(dev,
295 0,
296 "sm_cbu_ecc_uncorrected_err_count",
297 &g->ecc.gr.sm_cbu_uncorrected_err_count);
298
299 error |= nvgpu_gr_ecc_stat_create(dev,
300 0,
301 "sm_l1_data_ecc_corrected_err_count",
302 &g->ecc.gr.sm_l1_data_corrected_err_count);
303
304 error |= nvgpu_gr_ecc_stat_create(dev,
305 0,
306 "sm_l1_data_ecc_uncorrected_err_count",
307 &g->ecc.gr.sm_l1_data_uncorrected_err_count);
308
309 error |= nvgpu_gr_ecc_stat_create(dev,
310 0,
311 "sm_icache_ecc_corrected_err_count",
312 &g->ecc.gr.sm_icache_corrected_err_count);
313
314 error |= nvgpu_gr_ecc_stat_create(dev,
315 0,
316 "sm_icache_ecc_uncorrected_err_count",
317 &g->ecc.gr.sm_icache_uncorrected_err_count);
318
319 error |= nvgpu_gr_ecc_stat_create(dev,
320 0,
321 "gcc_l15_ecc_corrected_err_count",
322 &g->ecc.gr.gcc_l15_corrected_err_count);
323
324 error |= nvgpu_gr_ecc_stat_create(dev,
325 0,
326 "gcc_l15_ecc_uncorrected_err_count",
327 &g->ecc.gr.gcc_l15_uncorrected_err_count);
328
329 error |= nvgpu_ecc_stat_create(dev,
330 g->ltc_count,
331 0,
332 "ltc",
333 NULL,
334 "l2_cache_uncorrected_err_count",
335 &g->ecc.ltc.l2_cache_uncorrected_err_count);
336
337 error |= nvgpu_ecc_stat_create(dev,
338 g->ltc_count,
339 0,
340 "ltc",
341 NULL,
342 "l2_cache_corrected_err_count",
343 &g->ecc.ltc.l2_cache_corrected_err_count);
344
345 error |= nvgpu_ecc_stat_create(dev,
346 1,
347 0,
348 "gpc",
349 NULL,
350 "fecs_ecc_uncorrected_err_count",
351 &g->ecc.gr.fecs_uncorrected_err_count);
352
353 error |= nvgpu_ecc_stat_create(dev,
354 1,
355 0,
356 "gpc",
357 NULL,
358 "fecs_ecc_corrected_err_count",
359 &g->ecc.gr.fecs_corrected_err_count);
360
361 error |= nvgpu_ecc_stat_create(dev,
362 g->gr.gpc_count,
363 0,
364 "gpc",
365 NULL,
366 "gpccs_ecc_uncorrected_err_count",
367 &g->ecc.gr.gpccs_uncorrected_err_count);
368
369 error |= nvgpu_ecc_stat_create(dev,
370 g->gr.gpc_count,
371 0,
372 "gpc",
373 NULL,
374 "gpccs_ecc_corrected_err_count",
375 &g->ecc.gr.gpccs_corrected_err_count);
376
377 error |= nvgpu_ecc_stat_create(dev,
378 g->gr.gpc_count,
379 0,
380 "gpc",
381 NULL,
382 "mmu_l1tlb_ecc_uncorrected_err_count",
383 &g->ecc.gr.mmu_l1tlb_uncorrected_err_count);
384
385 error |= nvgpu_ecc_stat_create(dev,
386 g->gr.gpc_count,
387 0,
388 "gpc",
389 NULL,
390 "mmu_l1tlb_ecc_corrected_err_count",
391 &g->ecc.gr.mmu_l1tlb_corrected_err_count);
392
393 error |= nvgpu_ecc_stat_create(dev,
394 1,
395 0,
396 "eng",
397 NULL,
398 "mmu_l2tlb_ecc_uncorrected_err_count",
399 &g->ecc.fb.mmu_l2tlb_uncorrected_err_count);
400
401 error |= nvgpu_ecc_stat_create(dev,
402 1,
403 0,
404 "eng",
405 NULL,
406 "mmu_l2tlb_ecc_corrected_err_count",
407 &g->ecc.fb.mmu_l2tlb_corrected_err_count);
408
409 error |= nvgpu_ecc_stat_create(dev,
410 1,
411 0,
412 "eng",
413 NULL,
414 "mmu_hubtlb_ecc_uncorrected_err_count",
415 &g->ecc.fb.mmu_hubtlb_uncorrected_err_count);
416
417 error |= nvgpu_ecc_stat_create(dev,
418 1,
419 0,
420 "eng",
421 NULL,
422 "mmu_hubtlb_ecc_corrected_err_count",
423 &g->ecc.fb.mmu_hubtlb_corrected_err_count);
424
425 error |= nvgpu_ecc_stat_create(dev,
426 1,
427 0,
428 "eng",
429 NULL,
430 "mmu_fillunit_ecc_uncorrected_err_count",
431 &g->ecc.fb.mmu_fillunit_uncorrected_err_count);
432
433 error |= nvgpu_ecc_stat_create(dev,
434 1,
435 0,
436 "eng",
437 NULL,
438 "mmu_fillunit_ecc_corrected_err_count",
439 &g->ecc.fb.mmu_fillunit_corrected_err_count);
440
441 error |= nvgpu_ecc_stat_create(dev,
442 1,
443 0,
444 "eng",
445 NULL,
446 "pmu_ecc_uncorrected_err_count",
447 &g->ecc.pmu.pmu_uncorrected_err_count);
448
449 error |= nvgpu_ecc_stat_create(dev,
450 1,
451 0,
452 "eng",
453 NULL,
454 "pmu_ecc_corrected_err_count",
455 &g->ecc.pmu.pmu_corrected_err_count);
456
457 if (error)
458 dev_err(dev, "Failed to create gv11b sysfs attributes!\n");
459}
460
461void gr_gv11b_remove_sysfs(struct gk20a *g)
462{
463 struct device *dev = dev_from_gk20a(g);
464
465 if (!g->ecc.gr.sm_l1_tag_corrected_err_count.counters)
466 return;
467 gr_gp10b_remove_sysfs(g);
468
469 nvgpu_gr_ecc_stat_remove(dev,
470 0,
471 &g->ecc.gr.sm_l1_tag_corrected_err_count);
472
473 nvgpu_gr_ecc_stat_remove(dev,
474 0,
475 &g->ecc.gr.sm_l1_tag_uncorrected_err_count);
476
477 nvgpu_gr_ecc_stat_remove(dev,
478 0,
479 &g->ecc.gr.sm_cbu_corrected_err_count);
480
481 nvgpu_gr_ecc_stat_remove(dev,
482 0,
483 &g->ecc.gr.sm_cbu_uncorrected_err_count);
484
485 nvgpu_gr_ecc_stat_remove(dev,
486 0,
487 &g->ecc.gr.sm_l1_data_corrected_err_count);
488
489 nvgpu_gr_ecc_stat_remove(dev,
490 0,
491 &g->ecc.gr.sm_l1_data_uncorrected_err_count);
492
493 nvgpu_gr_ecc_stat_remove(dev,
494 0,
495 &g->ecc.gr.sm_icache_corrected_err_count);
496
497 nvgpu_gr_ecc_stat_remove(dev,
498 0,
499 &g->ecc.gr.sm_icache_uncorrected_err_count);
500
501 nvgpu_gr_ecc_stat_remove(dev,
502 0,
503 &g->ecc.gr.gcc_l15_corrected_err_count);
504
505 nvgpu_gr_ecc_stat_remove(dev,
506 0,
507 &g->ecc.gr.gcc_l15_uncorrected_err_count);
508
509 nvgpu_ecc_stat_remove(dev,
510 g->ltc_count,
511 0,
512 &g->ecc.ltc.l2_cache_uncorrected_err_count);
513
514 nvgpu_ecc_stat_remove(dev,
515 g->ltc_count,
516 0,
517 &g->ecc.ltc.l2_cache_corrected_err_count);
518
519 nvgpu_ecc_stat_remove(dev,
520 1,
521 0,
522 &g->ecc.gr.fecs_uncorrected_err_count);
523
524 nvgpu_ecc_stat_remove(dev,
525 1,
526 0,
527 &g->ecc.gr.fecs_corrected_err_count);
528
529 nvgpu_ecc_stat_remove(dev,
530 g->gr.gpc_count,
531 0,
532 &g->ecc.gr.gpccs_uncorrected_err_count);
533
534 nvgpu_ecc_stat_remove(dev,
535 g->gr.gpc_count,
536 0,
537 &g->ecc.gr.gpccs_corrected_err_count);
538
539 nvgpu_ecc_stat_remove(dev,
540 g->gr.gpc_count,
541 0,
542 &g->ecc.gr.mmu_l1tlb_uncorrected_err_count);
543
544 nvgpu_ecc_stat_remove(dev,
545 g->gr.gpc_count,
546 0,
547 &g->ecc.gr.mmu_l1tlb_corrected_err_count);
548
549 nvgpu_ecc_stat_remove(dev,
550 1,
551 0,
552 &g->ecc.fb.mmu_l2tlb_uncorrected_err_count);
553
554 nvgpu_ecc_stat_remove(dev,
555 1,
556 0,
557 &g->ecc.fb.mmu_l2tlb_corrected_err_count);
558
559 nvgpu_ecc_stat_remove(dev,
560 1,
561 0,
562 &g->ecc.fb.mmu_hubtlb_uncorrected_err_count);
563
564 nvgpu_ecc_stat_remove(dev,
565 1,
566 0,
567 &g->ecc.fb.mmu_hubtlb_corrected_err_count);
568
569 nvgpu_ecc_stat_remove(dev,
570 1,
571 0,
572 &g->ecc.fb.mmu_fillunit_uncorrected_err_count);
573
574 nvgpu_ecc_stat_remove(dev,
575 1,
576 0,
577 &g->ecc.fb.mmu_fillunit_corrected_err_count);
578
579 nvgpu_ecc_stat_remove(dev,
580 1,
581 0,
582 &g->ecc.pmu.pmu_uncorrected_err_count);
583
584 nvgpu_ecc_stat_remove(dev,
585 1,
586 0,
587 &g->ecc.pmu.pmu_corrected_err_count);
588}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 15:21:13 -0400