diff options
author | Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com> | 2018-12-13 06:59:20 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-06-30 13:07:26 -0400 |
commit | f56874aec2ec61f2c341b813cc76de5acc51ea12 (patch) | |
tree | efd3d6a3921c930a76bf0cb7011ca6b9809ed5f3 /drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |
parent | bbef4c6927a13a24821c43cb2b6af72f859f7deb (diff) |
gpu: nvgpu: add speculative barrier
Data can be speculativerly stored and
code flow can be hijacked.
To mitigate this problem insert a
speculation barrier.
Bug 200447167
Change-Id: Ia865ff2add8b30de49aa970715625b13e8f71c08
Signed-off-by: Ranjanikar Nikhil Prabhakarrao <rprabhakarra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1972221
(cherry picked from commit f0762ed4831b3fe6cc953a4a4ec26c2537dcb69f)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/1996052
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Deepak Nibade <dnibade@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/ioctl_dbg.c')
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index dc732dc5..0c9b10b5 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -314,6 +314,7 @@ static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state( | |||
314 | if (args->sm_error_state_record_size > 0) { | 314 | if (args->sm_error_state_record_size > 0) { |
315 | size_t write_size = sizeof(*sm_error_state); | 315 | size_t write_size = sizeof(*sm_error_state); |
316 | 316 | ||
317 | nvgpu_speculation_barrier(); | ||
317 | if (write_size > args->sm_error_state_record_size) | 318 | if (write_size > args->sm_error_state_record_size) |
318 | write_size = args->sm_error_state_record_size; | 319 | write_size = args->sm_error_state_record_size; |
319 | 320 | ||
@@ -361,6 +362,7 @@ static int nvgpu_dbg_timeout_enable(struct dbg_session_gk20a *dbg_s, | |||
361 | nvgpu_log(g, gpu_dbg_gpu_dbg, "Timeouts mode requested : %d", | 362 | nvgpu_log(g, gpu_dbg_gpu_dbg, "Timeouts mode requested : %d", |
362 | timeout_mode); | 363 | timeout_mode); |
363 | 364 | ||
365 | nvgpu_speculation_barrier(); | ||
364 | switch (timeout_mode) { | 366 | switch (timeout_mode) { |
365 | case NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE: | 367 | case NVGPU_DBG_GPU_IOCTL_TIMEOUT_ENABLE: |
366 | if (dbg_s->is_timeout_disabled == true) | 368 | if (dbg_s->is_timeout_disabled == true) |
@@ -917,6 +919,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
917 | ops_offset += num_ops; | 919 | ops_offset += num_ops; |
918 | } | 920 | } |
919 | 921 | ||
922 | nvgpu_speculation_barrier(); | ||
920 | nvgpu_kfree(g, linux_fragment); | 923 | nvgpu_kfree(g, linux_fragment); |
921 | 924 | ||
922 | /* enable powergate, if previously disabled */ | 925 | /* enable powergate, if previously disabled */ |
@@ -1007,6 +1010,7 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s, | |||
1007 | 1010 | ||
1008 | static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode) | 1011 | static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode) |
1009 | { | 1012 | { |
1013 | nvgpu_speculation_barrier(); | ||
1010 | switch (mode){ | 1014 | switch (mode){ |
1011 | case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW: | 1015 | case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW: |
1012 | return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW; | 1016 | return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW; |
@@ -1153,6 +1157,7 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | |||
1153 | goto clean_up; | 1157 | goto clean_up; |
1154 | } | 1158 | } |
1155 | 1159 | ||
1160 | nvgpu_speculation_barrier(); | ||
1156 | switch (action) { | 1161 | switch (action) { |
1157 | case NVGPU_DBG_GPU_SUSPEND_ALL_SMS: | 1162 | case NVGPU_DBG_GPU_SUSPEND_ALL_SMS: |
1158 | gr_gk20a_suspend_context(ch); | 1163 | gr_gk20a_suspend_context(ch); |
@@ -1366,6 +1371,7 @@ static int gk20a_dbg_gpu_events_ctrl(struct dbg_session_gk20a *dbg_s, | |||
1366 | return -EINVAL; | 1371 | return -EINVAL; |
1367 | } | 1372 | } |
1368 | 1373 | ||
1374 | nvgpu_speculation_barrier(); | ||
1369 | switch (args->cmd) { | 1375 | switch (args->cmd) { |
1370 | case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE: | 1376 | case NVGPU_DBG_GPU_EVENTS_CTRL_CMD_ENABLE: |
1371 | gk20a_dbg_gpu_events_enable(dbg_s); | 1377 | gk20a_dbg_gpu_events_enable(dbg_s); |
@@ -1536,6 +1542,7 @@ nvgpu_dbg_gpu_ioctl_suspend_resume_contexts(struct dbg_session_gk20a *dbg_s, | |||
1536 | if (err) | 1542 | if (err) |
1537 | return err; | 1543 | return err; |
1538 | 1544 | ||
1545 | nvgpu_speculation_barrier(); | ||
1539 | switch (args->action) { | 1546 | switch (args->action) { |
1540 | case NVGPU_DBG_GPU_SUSPEND_ALL_CONTEXTS: | 1547 | case NVGPU_DBG_GPU_SUSPEND_ALL_CONTEXTS: |
1541 | err = g->ops.gr.suspend_contexts(g, dbg_s, | 1548 | err = g->ops.gr.suspend_contexts(g, dbg_s, |
@@ -1627,6 +1634,7 @@ static int nvgpu_dbg_gpu_ioctl_access_fb_memory(struct dbg_session_gk20a *dbg_s, | |||
1627 | size -= access_size; | 1634 | size -= access_size; |
1628 | offset += access_size; | 1635 | offset += access_size; |
1629 | } | 1636 | } |
1637 | nvgpu_speculation_barrier(); | ||
1630 | 1638 | ||
1631 | fail_idle: | 1639 | fail_idle: |
1632 | gk20a_idle(g); | 1640 | gk20a_idle(g); |
@@ -1899,6 +1907,7 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | |||
1899 | struct gk20a *g = dbg_s->g; | 1907 | struct gk20a *g = dbg_s->g; |
1900 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | 1908 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; |
1901 | 1909 | ||
1910 | nvgpu_speculation_barrier(); | ||
1902 | switch (args->exception_type_mask) { | 1911 | switch (args->exception_type_mask) { |
1903 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | 1912 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: |
1904 | sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; | 1913 | sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL; |
@@ -1970,6 +1979,7 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
1970 | /* protect from threaded user space calls */ | 1979 | /* protect from threaded user space calls */ |
1971 | nvgpu_mutex_acquire(&dbg_s->ioctl_lock); | 1980 | nvgpu_mutex_acquire(&dbg_s->ioctl_lock); |
1972 | 1981 | ||
1982 | nvgpu_speculation_barrier(); | ||
1973 | switch (cmd) { | 1983 | switch (cmd) { |
1974 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: | 1984 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: |
1975 | err = dbg_bind_channel_gk20a(dbg_s, | 1985 | err = dbg_bind_channel_gk20a(dbg_s, |