gpu: nvgpu: enable HWPM Mode-E context switch

- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.

Bug 2106999

Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 23 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index 9c7608e9..d530492a 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -1039,12 +1039,33 @@ static int nvgpu_dbg_gpu_ioctl_smpc_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
         return  err;
 }
 
+/*
+ * Convert linux hwpm ctxsw mode type of the form of NVGPU_DBG_GPU_HWPM_CTXSW_MODE_*
+ * into common hwpm ctxsw mode type of the form of NVGPU_DBG_HWPM_CTXSW_MODE_*
+ */
+
+static u32 nvgpu_hwpm_ctxsw_mode_to_common_mode(u32 mode)
+{
+        switch (mode){
+        case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_NO_CTXSW:
+                return NVGPU_DBG_HWPM_CTXSW_MODE_NO_CTXSW;
+        case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW:
+                return NVGPU_DBG_HWPM_CTXSW_MODE_CTXSW;
+        case NVGPU_DBG_GPU_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW:
+                return NVGPU_DBG_HWPM_CTXSW_MODE_STREAM_OUT_CTXSW;
+        }
+
+        return mode;
+}
+
+
 static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
                                struct nvgpu_dbg_gpu_hwpm_ctxsw_mode_args *args)
 {
         int err;
         struct gk20a *g = dbg_s->g;
         struct channel_gk20a *ch_gk20a;
+        u32 mode = nvgpu_hwpm_ctxsw_mode_to_common_mode(args->mode);
 
         nvgpu_log_fn(g, "%s pm ctxsw mode = %d", g->name, args->mode);
 
@@ -1080,7 +1101,8 @@ static int nvgpu_dbg_gpu_ioctl_hwpm_ctxsw_mode(struct dbg_session_gk20a *dbg_s,
                 goto clean_up;
         }
         err = g->ops.gr.update_hwpm_ctxsw_mode(g, ch_gk20a, 0,
-                args->mode == NVGPU_DBG_GPU_HWPM_CTXSW_MODE_CTXSW);
+                mode);
+
         if (err)
                 nvgpu_err(g,
                         "error (%d) during pm ctxsw mode update", err);