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authorSourab Gupta <sourabg@nvidia.com>2018-08-03 10:31:47 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-08 05:00:16 -0400
commit32bcf21f5712fcd872b26ec70ad8987f7db4478f (patch)
tree9dfc6b740d5519d54b678171319c5ebf4d386914 /drivers/gpu/nvgpu/os/linux/ce2.c
parentb86fcdee3115b5bded24e27cc31ee06f8a0a3938 (diff)
gpu: nvgpu: move ce2.c to common code
ce2.c is free of all Linux'isms and can be moved to the common code, so that it can be used by other OS'es. VQRM-3705 Change-Id: Id4644a24188e9af2ba5f6875d1b8bc58b4450519 Signed-off-by: Sourab Gupta <sourabg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1792100 Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Lakshmanan M <lm@nvidia.com> Reviewed-by: Konsta Holtta <kholtta@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/os/linux/ce2.c')
-rw-r--r--drivers/gpu/nvgpu/os/linux/ce2.c155
1 files changed, 0 insertions, 155 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ce2.c b/drivers/gpu/nvgpu/os/linux/ce2.c
deleted file mode 100644
index 0b43c0d1..00000000
--- a/drivers/gpu/nvgpu/os/linux/ce2.c
+++ /dev/null
@@ -1,155 +0,0 @@
1/*
2 * Copyright (c) 2017, NVIDIA Corporation. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17#include <nvgpu/types.h>
18#include <nvgpu/channel.h>
19
20#include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
21
22#include "gk20a/ce2_gk20a.h"
23#include "gk20a/gk20a.h"
24#include "channel.h"
25
26static inline int gk20a_get_valid_launch_flags(struct gk20a *g, int launch_flags)
27{
28 /* there is no local memory available,
29 don't allow local memory related CE flags */
30 if (!g->mm.vidmem.size) {
31 launch_flags &= ~(NVGPU_CE_SRC_LOCATION_LOCAL_FB |
32 NVGPU_CE_DST_LOCATION_LOCAL_FB);
33 }
34 return launch_flags;
35}
36
37int gk20a_ce_execute_ops(struct gk20a *g,
38 u32 ce_ctx_id,
39 u64 src_buf,
40 u64 dst_buf,
41 u64 size,
42 unsigned int payload,
43 int launch_flags,
44 int request_operation,
45 u32 submit_flags,
46 struct gk20a_fence **gk20a_fence_out)
47{
48 int ret = -EPERM;
49 struct gk20a_ce_app *ce_app = &g->ce_app;
50 struct gk20a_gpu_ctx *ce_ctx, *ce_ctx_save;
51 bool found = false;
52 u32 *cmd_buf_cpu_va;
53 u64 cmd_buf_gpu_va = 0;
54 u32 methodSize;
55 u32 cmd_buf_read_offset;
56 u32 dma_copy_class;
57 struct nvgpu_gpfifo_entry gpfifo;
58 struct nvgpu_channel_fence fence = {0, 0};
59 struct gk20a_fence *ce_cmd_buf_fence_out = NULL;
60
61 if (!ce_app->initialised ||ce_app->app_state != NVGPU_CE_ACTIVE)
62 goto end;
63
64 nvgpu_mutex_acquire(&ce_app->app_mutex);
65
66 nvgpu_list_for_each_entry_safe(ce_ctx, ce_ctx_save,
67 &ce_app->allocated_contexts, gk20a_gpu_ctx, list) {
68 if (ce_ctx->ctx_id == ce_ctx_id) {
69 found = true;
70 break;
71 }
72 }
73
74 nvgpu_mutex_release(&ce_app->app_mutex);
75
76 if (!found) {
77 ret = -EINVAL;
78 goto end;
79 }
80
81 if (ce_ctx->gpu_ctx_state != NVGPU_CE_GPU_CTX_ALLOCATED) {
82 ret = -ENODEV;
83 goto end;
84 }
85
86 nvgpu_mutex_acquire(&ce_ctx->gpu_ctx_mutex);
87
88 ce_ctx->cmd_buf_read_queue_offset %= NVGPU_CE_MAX_INFLIGHT_JOBS;
89
90 cmd_buf_read_offset = (ce_ctx->cmd_buf_read_queue_offset *
91 (NVGPU_CE_MAX_COMMAND_BUFF_BYTES_PER_KICKOFF / sizeof(u32)));
92
93 cmd_buf_cpu_va = (u32 *)ce_ctx->cmd_buf_mem.cpu_va;
94
95 if (ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset]) {
96 struct gk20a_fence **prev_post_fence =
97 &ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset];
98
99 ret = gk20a_fence_wait(g, *prev_post_fence,
100 gk20a_get_gr_idle_timeout(g));
101
102 gk20a_fence_put(*prev_post_fence);
103 *prev_post_fence = NULL;
104 if (ret)
105 goto noop;
106 }
107
108 cmd_buf_gpu_va = (ce_ctx->cmd_buf_mem.gpu_va + (u64)(cmd_buf_read_offset *sizeof(u32)));
109
110 dma_copy_class = g->ops.get_litter_value(g, GPU_LIT_DMA_COPY_CLASS);
111 methodSize = gk20a_ce_prepare_submit(src_buf,
112 dst_buf,
113 size,
114 &cmd_buf_cpu_va[cmd_buf_read_offset],
115 NVGPU_CE_MAX_COMMAND_BUFF_BYTES_PER_KICKOFF,
116 payload,
117 gk20a_get_valid_launch_flags(g, launch_flags),
118 request_operation,
119 dma_copy_class);
120
121 if (methodSize) {
122 /* store the element into gpfifo */
123 gpfifo.entry0 =
124 u64_lo32(cmd_buf_gpu_va);
125 gpfifo.entry1 =
126 (u64_hi32(cmd_buf_gpu_va) |
127 pbdma_gp_entry1_length_f(methodSize));
128
129 /* take always the postfence as it is needed for protecting the ce context */
130 submit_flags |= NVGPU_SUBMIT_FLAGS_FENCE_GET;
131
132 nvgpu_smp_wmb();
133
134 ret = nvgpu_submit_channel_gpfifo_kernel(ce_ctx->ch, &gpfifo,
135 1, submit_flags, &fence, &ce_cmd_buf_fence_out);
136
137 if (!ret) {
138 ce_ctx->postfences[ce_ctx->cmd_buf_read_queue_offset] =
139 ce_cmd_buf_fence_out;
140 if (gk20a_fence_out) {
141 gk20a_fence_get(ce_cmd_buf_fence_out);
142 *gk20a_fence_out = ce_cmd_buf_fence_out;
143 }
144
145 /* Next available command buffer queue Index */
146 ++ce_ctx->cmd_buf_read_queue_offset;
147 }
148 } else {
149 ret = -ENOMEM;
150 }
151noop:
152 nvgpu_mutex_release(&ce_ctx->gpu_ctx_mutex);
153end:
154 return ret;
155}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-15 23:59:40 -0400