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| author | Tejal Kudav <tkudav@nvidia.com> | 2018-08-10 06:58:21 -0400 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-31 14:23:25 -0400 |
| commit | 8c8cdacf7a022d1326ec519daa8b8da174aa8f3d (patch) | |
| tree | 8e8b93c3b82e18c6178d645224b1fb23a33bb32e /drivers/gpu/nvgpu/lpwr | |
| parent | 90f268963c93025bdbb28a5a2b502cb738d5630d (diff) | |
gpu: nvgpu: Use reset_enum to get mc engine mask
Currently, we need to include the MC hardware header in nvlink file
to generate reset mask.
We can use the reset_enum present in DEVICE_INFO table's IOCTRL entry
which is meant to index into NV_PMC_ENABLE_DEVICE register bitfields.
This allows us to not #include the MC hardware header in nvlink IP
file.
JIRA NVGPU-966
Change-Id: I037498038b12f795ee444916fb586355ebf04bb3
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1796819
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr')
0 files changed, 0 insertions, 0 deletions