Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel

Merge T186 - gp10b/gp106 code into common nvgpu repo

Bug 200266498

Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>

4 files changed, 690 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
new file mode 100644
index 00000000..4f8d2eec
--- /dev/null
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+#include "gp106/pmu_gp106.h"
+#include "gk20a/pmu_api.h"
+#include "gm206/bios_gm206.h"
+#include "pstate/pstate.h"
+#include "include/bios.h"
+#include "perf/perf.h"
+#include "lpwr.h"
+
+static int get_lpwr_idx_table(struct gk20a *g)
+{
+        u32 *lpwr_idx_table_ptr;
+        u8 *entry_addr;
+        u32 idx;
+        struct nvgpu_lpwr_bios_idx_data *pidx_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.idx;
+        struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 };
+        struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 };
+
+        if (g->ops.bios.get_perf_table_ptrs) {
+                lpwr_idx_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g,
+                        g->bios.perf_token, LOWPOWER_TABLE);
+                if (lpwr_idx_table_ptr == NULL)
+                        return -EINVAL;
+        } else
+                 return -EINVAL;
+
+        memcpy(&header, lpwr_idx_table_ptr,
+                sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header));
+
+        if (header.entry_count >= LPWR_VBIOS_IDX_ENTRY_COUNT_MAX)
+                return -EINVAL;
+
+        pidx_data->base_sampling_period = (u16)header.base_sampling_period;
+
+        /* Parse the LPWR Index Table entries.*/
+        for (idx = 0; idx < header.entry_count; idx++) {
+                entry_addr = (u8 *)lpwr_idx_table_ptr + header.header_size +
+                        (idx * header.entry_size);
+
+                memcpy(&entry, entry_addr,
+                        sizeof(struct nvgpu_bios_lpwr_idx_table_1x_entry));
+
+                pidx_data->entry[idx].pcie_idx = entry.pcie_idx;
+                pidx_data->entry[idx].gr_idx = entry.gr_idx;
+                pidx_data->entry[idx].ms_idx = entry.ms_idx;
+                pidx_data->entry[idx].di_idx = entry.di_idx;
+                pidx_data->entry[idx].gc6_idx = entry.gc6_idx;
+
+        }
+
+        return 0;
+}
+
+static int get_lpwr_gr_table(struct gk20a *g)
+{
+        u32 *lpwr_gr_table_ptr;
+        u8 *entry_addr;
+        u32 idx;
+        struct nvgpu_lpwr_bios_gr_data *pgr_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.gr;
+        struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 };
+        struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 };
+
+        if (g->ops.bios.get_perf_table_ptrs) {
+                lpwr_gr_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g,
+                        g->bios.perf_token, LOWPOWER_GR_TABLE);
+                if (lpwr_gr_table_ptr == NULL)
+                        return -EINVAL;
+        } else
+                 return -EINVAL;
+
+        memcpy(&header, lpwr_gr_table_ptr,
+                sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header));
+
+        /* Parse the LPWR Index Table entries.*/
+        for (idx = 0; idx < header.entry_count; idx++) {
+                entry_addr = (u8 *)lpwr_gr_table_ptr + header.header_size +
+                        (idx * header.entry_size);
+
+                memcpy(&entry, entry_addr,
+                        sizeof(struct nvgpu_bios_lpwr_gr_table_1x_entry));
+
+                if (BIOS_GET_FIELD(entry.feautre_mask,
+                        NV_VBIOS_LPWR_MS_FEATURE_MASK_MS)) {
+                        pgr_data->entry[idx].gr_enabled = true;
+
+                        pgr_data->entry[idx].feature_mask =
+                                NVGPU_PMU_GR_FEATURE_MASK_ALL;
+
+                        if (!BIOS_GET_FIELD(entry.feautre_mask,
+                                NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG))
+                                pgr_data->entry[idx].feature_mask &=
+                                        ~NVGPU_PMU_GR_FEATURE_MASK_RPPG;
+                }
+
+        }
+
+        return 0;
+}
+
+static int get_lpwr_ms_table(struct gk20a *g)
+{
+        u32 *lpwr_ms_table_ptr;
+        u8 *entry_addr;
+        u32 idx;
+        struct nvgpu_lpwr_bios_ms_data *pms_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.ms;
+        struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 };
+        struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 };
+
+        if (g->ops.bios.get_perf_table_ptrs) {
+                lpwr_ms_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g,
+                        g->bios.perf_token, LOWPOWER_MS_TABLE);
+                if (lpwr_ms_table_ptr == NULL)
+                        return -EINVAL;
+        } else
+                 return -EINVAL;
+
+        memcpy(&header, lpwr_ms_table_ptr,
+                sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header));
+
+        if (header.entry_count >= LPWR_VBIOS_MS_ENTRY_COUNT_MAX)
+                return -EINVAL;
+
+        pms_data->default_entry_idx = (u8)header.default_entry_idx;
+
+        pms_data->idle_threshold_us = (u32)(header.idle_threshold_us * 10);
+
+        /* Parse the LPWR MS Table entries.*/
+        for (idx = 0; idx < header.entry_count; idx++) {
+                entry_addr = (u8 *)lpwr_ms_table_ptr + header.header_size +
+                        (idx * header.entry_size);
+
+                memcpy(&entry, entry_addr,
+                        sizeof(struct nvgpu_bios_lpwr_ms_table_1x_entry));
+
+                if (BIOS_GET_FIELD(entry.feautre_mask,
+                        NV_VBIOS_LPWR_MS_FEATURE_MASK_MS)) {
+                        pms_data->entry[idx].ms_enabled = true;
+
+                        pms_data->entry[idx].feature_mask =
+                                NVGPU_PMU_MS_FEATURE_MASK_ALL;
+
+                        if (!BIOS_GET_FIELD(entry.feautre_mask,
+                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING))
+                                pms_data->entry[idx].feature_mask &=
+                                        ~NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING;
+
+                        if (!BIOS_GET_FIELD(entry.feautre_mask,
+                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR))
+                                pms_data->entry[idx].feature_mask &=
+                                        ~NVGPU_PMU_MS_FEATURE_MASK_SW_ASR;
+
+                        if (!BIOS_GET_FIELD(entry.feautre_mask,
+                                NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG))
+                                pms_data->entry[idx].feature_mask &=
+                                        ~NVGPU_PMU_MS_FEATURE_MASK_RPPG;
+                }
+
+                pms_data->entry[idx].dynamic_current_logic =
+                                entry.dynamic_current_logic;
+
+                pms_data->entry[idx].dynamic_current_sram =
+                                entry.dynamic_current_sram;
+        }
+
+        return 0;
+}
+
+u32 nvgpu_lpwr_pg_setup(struct gk20a *g)
+{
+        u32 err = 0;
+
+        gk20a_dbg_fn("");
+
+        err = get_lpwr_gr_table(g);
+        if (err)
+                return err;
+
+        err = get_lpwr_ms_table(g);
+        if (err)
+                return err;
+
+        err = get_lpwr_idx_table(g);
+
+        return err;
+}
+
+static void nvgpu_pmu_handle_param_lpwr_msg(struct gk20a *g,
+                struct pmu_msg *msg, void *param,
+                u32 handle, u32 status)
+{
+        u32 *ack_status = param;
+
+        gk20a_dbg_fn("");
+
+        if (status != 0) {
+                gk20a_err(dev_from_gk20a(g), "LWPR PARAM cmd aborted");
+                return;
+        }
+
+        *ack_status = 1;
+
+        gp106_dbg_pmu("lpwr-param is acknowledged from PMU %x",
+                        msg->msg.pg.msg_type);
+}
+
+int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
+{
+        struct pmu_cmd cmd;
+        u32 seq, status = 0;
+        u32 payload = NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED;
+        struct clk_set_info *pstate_info;
+        u32 ack_status = 0;
+
+        gk20a_dbg_fn("");
+
+        pstate_info = pstate_get_clk_set_info(g, pstate,
+                        clkwhich_mclk);
+        if (!pstate_info)
+                return -EINVAL;
+
+        if (pstate_info->max_mhz >
+                        MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ)
+                payload |=
+                        NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED;
+
+        if (payload != g->perf_pmu.lpwr.mclk_change_cache) {
+                g->perf_pmu.lpwr.mclk_change_cache = payload;
+
+                cmd.hdr.unit_id = PMU_UNIT_PG;
+                cmd.hdr.size = PMU_CMD_HDR_SIZE +
+                        sizeof(struct pmu_pg_cmd_mclk_change);
+                cmd.cmd.pg.mclk_change.cmd_type =
+                        PMU_PG_CMD_ID_PG_PARAM;
+                cmd.cmd.pg.mclk_change.cmd_id =
+                        PMU_PG_PARAM_CMD_MCLK_CHANGE;
+                cmd.cmd.pg.mclk_change.data = payload;
+
+                gp106_dbg_pmu("cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
+                status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
+                        PMU_COMMAND_QUEUE_HPQ,
+                        nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
+
+                pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+                        &ack_status, 1);
+                if (ack_status == 0) {
+                        status = -EINVAL;
+                        gk20a_err(dev_from_gk20a(g), "MCLK-CHANGE ACK failed");
+                }
+        }
+
+        return status;
+}
+
+u32 nvgpu_lpwr_post_init(struct gk20a *g)
+{
+        struct pmu_cmd cmd;
+        u32 seq;
+        u32 status = 0;
+        u32 ack_status = 0;
+
+        memset(&cmd, 0, sizeof(struct pmu_cmd));
+        cmd.hdr.unit_id = PMU_UNIT_PG;
+        cmd.hdr.size   = PMU_CMD_HDR_SIZE +
+                sizeof(struct pmu_pg_cmd_post_init_param);
+
+        cmd.cmd.pg.post_init.cmd_type =
+                PMU_PG_CMD_ID_PG_PARAM;
+        cmd.cmd.pg.post_init.cmd_id =
+                PMU_PG_PARAM_CMD_POST_INIT;
+
+        gp106_dbg_pmu("cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
+        status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
+                PMU_COMMAND_QUEUE_LPQ,
+                nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
+
+        pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+                &ack_status, 1);
+        if (ack_status == 0) {
+                status = -EINVAL;
+                gk20a_err(dev_from_gk20a(g), "post-init ack failed");
+        }
+
+        return status;
+}
+
+u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num)
+{
+        struct nvgpu_lpwr_bios_ms_data *pms_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.ms;
+        struct nvgpu_lpwr_bios_idx_data *pidx_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.idx;
+        struct pstate *pstate = pstate_find(g, pstate_num);
+        u32 ms_idx;
+
+        gk20a_dbg_fn("");
+
+        if (!pstate)
+                return 0;
+
+        ms_idx = pidx_data->entry[pstate->lpwr_entry_idx].ms_idx;
+        if (pms_data->entry[ms_idx].ms_enabled)
+                return 1;
+        else
+                return 0;
+}
+
+u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
+{
+        struct nvgpu_lpwr_bios_gr_data *pgr_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.gr;
+        struct nvgpu_lpwr_bios_idx_data *pidx_data =
+                        &g->perf_pmu.lpwr.lwpr_bios_data.idx;
+        struct pstate *pstate = pstate_find(g, pstate_num);
+        u32 idx;
+
+        gk20a_dbg_fn("");
+
+        if (!pstate)
+                return 0;
+
+        idx = pidx_data->entry[pstate->lpwr_entry_idx].gr_idx;
+        if (pgr_data->entry[idx].gr_enabled)
+                return 1;
+        else
+                return 0;
+}
+
+
+int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        u32  status = 0;
+        u32 is_mscg_supported = 0;
+        u32 is_rppg_supported = 0;
+        u32 present_pstate = 0;
+
+        gk20a_dbg_fn("");
+
+        if (pstate_lock)
+                nvgpu_clk_arb_pstate_change_lock(g, true);
+        mutex_lock(&pmu->pg_mutex);
+
+        present_pstate = nvgpu_clk_arb_get_current_pstate(g);
+
+        is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
+                        present_pstate);
+        if (is_mscg_supported && g->mscg_enabled) {
+                if (!pmu->mscg_stat)
+                        pmu->mscg_stat = PMU_MSCG_ENABLED;
+        }
+
+        is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g,
+                        present_pstate);
+        if (is_rppg_supported) {
+                if (support_gk20a_pmu(g->dev) && g->elpg_enabled)
+                        status = gk20a_pmu_enable_elpg(g);
+        }
+
+        mutex_unlock(&pmu->pg_mutex);
+        if (pstate_lock)
+                nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        return status;
+}
+
+int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock)
+{
+        struct pmu_gk20a *pmu = &g->pmu;
+        int status = 0;
+        u32 is_mscg_supported = 0;
+        u32 is_rppg_supported = 0;
+        u32 present_pstate = 0;
+
+        gk20a_dbg_fn("");
+
+        if (pstate_lock)
+                nvgpu_clk_arb_pstate_change_lock(g, true);
+        mutex_lock(&pmu->pg_mutex);
+
+        present_pstate = nvgpu_clk_arb_get_current_pstate(g);
+
+        is_rppg_supported = nvgpu_lpwr_is_rppg_supported(g,
+                        present_pstate);
+        if (is_rppg_supported) {
+                if (support_gk20a_pmu(g->dev) && g->elpg_enabled) {
+                        status = gk20a_pmu_disable_elpg(g);
+                        if (status)
+                                goto exit_unlock;
+                }
+        }
+
+        is_mscg_supported = nvgpu_lpwr_is_mscg_supported(g,
+                        present_pstate);
+        if (is_mscg_supported && g->mscg_enabled) {
+                if (pmu->mscg_stat)
+                        pmu->mscg_stat = PMU_MSCG_DISABLED;
+        }
+
+exit_unlock:
+        mutex_unlock(&pmu->pg_mutex);
+        if (pstate_lock)
+                nvgpu_clk_arb_pstate_change_lock(g, false);
+
+        gk20a_dbg_fn("done");
+        return status;
+}
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.h b/drivers/gpu/nvgpu/lpwr/lpwr.h
new file mode 100644
index 00000000..6b3259df
--- /dev/null
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _MSCG_H_
+#define _MSCG_H_
+
+#define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ   540
+
+#define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT(0x1)
+#define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT(0x3)
+
+#define LPWR_ENTRY_COUNT_MAX 0x06
+
+#define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
+
+#define LPWR_VBIOS_IDX_ENTRY_RSVD \
+        (LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1)
+
+#define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT    (500)
+
+struct nvgpu_lpwr_bios_idx_entry {
+        u8 pcie_idx;
+        u8 gr_idx;
+        u8 ms_idx;
+        u8 di_idx;
+        u8 gc6_idx;
+};
+
+struct nvgpu_lpwr_bios_idx_data {
+        u16 base_sampling_period;
+        struct nvgpu_lpwr_bios_idx_entry entry[LPWR_VBIOS_IDX_ENTRY_COUNT_MAX];
+};
+
+#define LPWR_VBIOS_MS_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
+
+struct nvgpu_lpwr_bios_ms_entry {
+        bool ms_enabled;
+        u32 feature_mask;
+        u32 asr_efficiency_thresholdl;
+        u16 dynamic_current_logic;
+        u16 dynamic_current_sram;
+};
+
+struct nvgpu_lpwr_bios_ms_data {
+        u8 default_entry_idx;
+        u32 idle_threshold_us;
+        struct nvgpu_lpwr_bios_ms_entry entry[LPWR_VBIOS_MS_ENTRY_COUNT_MAX];
+};
+
+#define LPWR_VBIOS_GR_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX)
+
+struct nvgpu_lpwr_bios_gr_entry {
+        bool  gr_enabled;
+        u32   feature_mask;
+};
+
+struct nvgpu_lpwr_bios_gr_data {
+        u8 default_entry_idx;
+        u32 idle_threshold_us;
+        u8 adaptive_gr_multiplier;
+        struct nvgpu_lpwr_bios_gr_entry  entry[LPWR_VBIOS_GR_ENTRY_COUNT_MAX];
+};
+
+struct nvgpu_lpwr_bios_data {
+        struct nvgpu_lpwr_bios_idx_data idx;
+        struct nvgpu_lpwr_bios_ms_data ms;
+        struct nvgpu_lpwr_bios_gr_data gr;
+};
+
+struct obj_lwpr {
+        struct nvgpu_lpwr_bios_data lwpr_bios_data;
+        u32 mclk_change_cache;
+};
+
+u32 nvgpu_lpwr_pg_setup(struct gk20a *g);
+int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate);
+int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock);
+int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock);
+u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num);
+u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num);
+u32 nvgpu_lpwr_post_init(struct gk20a *g);
+
+#endif
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c
new file mode 100644
index 00000000..40e857ee
--- /dev/null
+++ b/drivers/gpu/nvgpu/lpwr/rppg.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include "gk20a/gk20a.h"
+#include "gk20a/pmu_gk20a.h"
+#include "gp106/pmu_gp106.h"
+#include "gk20a/pmu_api.h"
+#include "gm206/bios_gm206.h"
+#include "pstate/pstate.h"
+#include "include/bios.h"
+#include "pmuif/gpmuif_pg_rppg.h"
+
+static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
+        void *param, u32 handle, u32 status)
+{
+
+        u8 ctrlId = NV_PMU_RPPG_CTRL_ID_MAX;
+        u32 *success = param;
+
+        if (status == 0) {
+                switch (msg->msg.pg.rppg_msg.cmn.msg_id) {
+                case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK:
+                        ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id;
+                        *success = 1;
+                        gp106_dbg_pmu("RPPG is acknowledged from PMU %x",
+                                msg->msg.pg.msg_type);
+                break;
+                }
+        }
+
+        gp106_dbg_pmu("RPPG is acknowledged from PMU %x",
+                                msg->msg.pg.msg_type);
+}
+
+static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd)
+{
+        struct pmu_cmd cmd;
+        u32 seq;
+        u32 status = 0;
+        u32 success = 0;
+
+        memset(&cmd, 0, sizeof(struct pmu_cmd));
+        cmd.hdr.unit_id = PMU_UNIT_PG;
+        cmd.hdr.size   = PMU_CMD_HDR_SIZE +
+                        sizeof(struct nv_pmu_rppg_cmd);
+
+        cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG;
+        cmd.cmd.pg.rppg_cmd.cmn.cmd_id   = prppg_cmd->cmn.cmd_id;
+
+        switch (prppg_cmd->cmn.cmd_id) {
+        case NV_PMU_RPPG_CMD_ID_INIT:
+                break;
+        case NV_PMU_RPPG_CMD_ID_INIT_CTRL:
+                cmd.cmd.pg.rppg_cmd.init_ctrl.ctrl_id =
+                        prppg_cmd->init_ctrl.ctrl_id;
+                cmd.cmd.pg.rppg_cmd.init_ctrl.domain_id =
+                        prppg_cmd->init_ctrl.domain_id;
+                break;
+        case NV_PMU_RPPG_CMD_ID_STATS_RESET:
+                cmd.cmd.pg.rppg_cmd.stats_reset.ctrl_id =
+                        prppg_cmd->stats_reset.ctrl_id;
+                break;
+        default:
+                gk20a_err(dev_from_gk20a(g), "Inivalid RPPG command %d",
+                        prppg_cmd->cmn.cmd_id);
+                return -1;
+        }
+
+        status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
+                        pmu_handle_rppg_init_msg, &success, &seq, ~0);
+        if (status) {
+                gk20a_err(dev_from_gk20a(g), "Unable to submit parameter command %d",
+                        prppg_cmd->cmn.cmd_id);
+                goto exit;
+        }
+
+        if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) {
+                pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g),
+                        &success, 1);
+                if (success == 0) {
+                        status = -EINVAL;
+                        gk20a_err(dev_from_gk20a(g), "Ack for the parameter command %x",
+                                prppg_cmd->cmn.cmd_id);
+                }
+        }
+
+exit:
+        return status;
+}
+
+static u32 rppg_init(struct gk20a *g)
+{
+        struct nv_pmu_rppg_cmd rppg_cmd;
+
+        rppg_cmd.init.cmd_id = NV_PMU_RPPG_CMD_ID_INIT;
+
+        return rppg_send_cmd(g, &rppg_cmd);
+}
+
+static u32 rppg_ctrl_init(struct gk20a *g, u8 ctrl_id)
+{
+        struct nv_pmu_rppg_cmd rppg_cmd;
+
+        rppg_cmd.init_ctrl.cmd_id  = NV_PMU_RPPG_CMD_ID_INIT_CTRL;
+        rppg_cmd.init_ctrl.ctrl_id = ctrl_id;
+
+        switch (ctrl_id) {
+        case NV_PMU_RPPG_CTRL_ID_GR:
+        case NV_PMU_RPPG_CTRL_ID_MS:
+                rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX;
+                break;
+        }
+
+        return rppg_send_cmd(g, &rppg_cmd);
+}
+
+u32 init_rppg(struct gk20a *g)
+{
+        u32 status;
+
+        status = rppg_init(g);
+        if (status != 0) {
+                gk20a_err(dev_from_gk20a(g),
+                        "Failed to initialize RPPG in PMU: 0x%08x", status);
+                return status;
+        }
+
+
+        status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR);
+        if (status != 0) {
+                gk20a_err(dev_from_gk20a(g),
+                        "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x",
+                        status);
+                return status;
+        }
+
+        status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS);
+        if (status != 0) {
+                gk20a_err(dev_from_gk20a(g),
+                        "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x",
+                        status);
+                return status;
+        }
+
+        return status;
+}
+
+
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.h b/drivers/gpu/nvgpu/lpwr/rppg.h
new file mode 100644
index 00000000..8dc8d36c
--- /dev/null
+++ b/drivers/gpu/nvgpu/lpwr/rppg.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+#ifndef _RPPG_H_
+#define _RPPG_H_
+
+u32 init_rppg(struct gk20a *g);
+#endif