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authorMahantesh Kumbar <mkumbar@nvidia.com>2017-05-10 11:05:24 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-05 02:05:18 -0400
commit673dd971600b26131c0afdb221e13c080da022fd (patch)
tree7c8416ac2ef61891812773d55c8c8dc61da824aa /drivers/gpu/nvgpu/lpwr
parent7668ccb2a2e4a8c13d82b427c65be79c725afe08 (diff)
gpu: nvgpu: moved & renamed "struct pmu_gk20a"
- Renamed "struct pmu_gk20a" to "struct nvgpu_pmu" then moved to file "pmu.h" under folder "drivers/gpu/nvgpu/include/nvgpu/" - Included header file "pmu.h" to dependent file & removed "pmu_gk20a.h" include if its usage is not present. - Replaced "struct pmu_gk20a" with "struct nvgpu_pmu" in dependent source & header files. JIRA NVGPU-56 Change-Id: Ia3c606616831027093d5c216959c6a40d7c2632e Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1479209 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr')
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c13
-rw-r--r--drivers/gpu/nvgpu/lpwr/rppg.c8
2 files changed, 10 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 099c81d6..85acfd67 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -12,10 +12,9 @@
12 */ 12 */
13 13
14#include <nvgpu/bios.h> 14#include <nvgpu/bios.h>
15#include <nvgpu/pmu.h>
15 16
16#include "gk20a/gk20a.h" 17#include "gk20a/gk20a.h"
17#include "gk20a/pmu_gk20a.h"
18#include "gp106/pmu_gp106.h"
19#include "gm206/bios_gm206.h" 18#include "gm206/bios_gm206.h"
20#include "pstate/pstate.h" 19#include "pstate/pstate.h"
21#include "perf/perf.h" 20#include "perf/perf.h"
@@ -207,7 +206,7 @@ static void nvgpu_pmu_handle_param_lpwr_msg(struct gk20a *g,
207 206
208 *ack_status = 1; 207 *ack_status = 1;
209 208
210 gp106_dbg_pmu("lpwr-param is acknowledged from PMU %x", 209 nvgpu_pmu_dbg(g, "lpwr-param is acknowledged from PMU %x",
211 msg->msg.pg.msg_type); 210 msg->msg.pg.msg_type);
212} 211}
213 212
@@ -243,7 +242,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
243 PMU_PG_PARAM_CMD_MCLK_CHANGE; 242 PMU_PG_PARAM_CMD_MCLK_CHANGE;
244 cmd.cmd.pg.mclk_change.data = payload; 243 cmd.cmd.pg.mclk_change.data = payload;
245 244
246 gp106_dbg_pmu("cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE"); 245 nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
247 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, 246 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
248 PMU_COMMAND_QUEUE_HPQ, 247 PMU_COMMAND_QUEUE_HPQ,
249 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); 248 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
@@ -276,7 +275,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
276 cmd.cmd.pg.post_init.cmd_id = 275 cmd.cmd.pg.post_init.cmd_id =
277 PMU_PG_PARAM_CMD_POST_INIT; 276 PMU_PG_PARAM_CMD_POST_INIT;
278 277
279 gp106_dbg_pmu("cmd post post-init PMU_PG_PARAM_CMD_POST_INIT"); 278 nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
280 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, 279 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL,
281 PMU_COMMAND_QUEUE_LPQ, 280 PMU_COMMAND_QUEUE_LPQ,
282 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); 281 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
@@ -336,7 +335,7 @@ u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num)
336 335
337int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock) 336int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
338{ 337{
339 struct pmu_gk20a *pmu = &g->pmu; 338 struct nvgpu_pmu *pmu = &g->pmu;
340 u32 status = 0; 339 u32 status = 0;
341 u32 is_mscg_supported = 0; 340 u32 is_mscg_supported = 0;
342 u32 is_rppg_supported = 0; 341 u32 is_rppg_supported = 0;
@@ -376,7 +375,7 @@ int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock)
376 375
377int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock) 376int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock)
378{ 377{
379 struct pmu_gk20a *pmu = &g->pmu; 378 struct nvgpu_pmu *pmu = &g->pmu;
380 int status = 0; 379 int status = 0;
381 u32 is_mscg_supported = 0; 380 u32 is_mscg_supported = 0;
382 u32 is_rppg_supported = 0; 381 u32 is_rppg_supported = 0;
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c
index 59948f35..553457f7 100644
--- a/drivers/gpu/nvgpu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/lpwr/rppg.c
@@ -11,9 +11,9 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/pmu.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "gk20a/pmu_gk20a.h"
16#include "gp106/pmu_gp106.h"
17#include "gm206/bios_gm206.h" 17#include "gm206/bios_gm206.h"
18#include "pstate/pstate.h" 18#include "pstate/pstate.h"
19 19
@@ -29,13 +29,13 @@ static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
29 case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK: 29 case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK:
30 ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id; 30 ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id;
31 *success = 1; 31 *success = 1;
32 gp106_dbg_pmu("RPPG is acknowledged from PMU %x", 32 nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
33 msg->msg.pg.msg_type); 33 msg->msg.pg.msg_type);
34 break; 34 break;
35 } 35 }
36 } 36 }
37 37
38 gp106_dbg_pmu("RPPG is acknowledged from PMU %x", 38 nvgpu_pmu_dbg(g, "RPPG is acknowledged from PMU %x",
39 msg->msg.pg.msg_type); 39 msg->msg.pg.msg_type);
40} 40}
41 41