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authorMahantesh Kumbar <mkumbar@nvidia.com>2017-06-23 07:40:13 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-29 16:29:52 -0400
commit268721975c6c72418e2282126e7f594f62e6e118 (patch)
tree62c64561775f42513a9dda74244f613dc5a59543 /drivers/gpu/nvgpu/lpwr/rppg.h
parent97aea977e25c17ecb44448eb19dc15e740036958 (diff)
gpu: nvgpu: PMU reset reorg
- nvgpu_pmu_reset() as pmu reset for all chips & removed gk20a_pmu_reset() & gp106_pmu_reset() along with dependent code. - Created ops to do PMU engine reset & to know the engine reset status - Removed pmu.reset ops & replaced with nvgpu_flcn_reset(pmu->flcn) - Moved sec2 reset to sec2_gp106 from pmu_gp106 & cleaned PMU code part of sec2. JIRA NVGPU-99 Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1507881 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
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