diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:01:00 -0500 |
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committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 05:35:06 -0500 |
commit | 7a81883a0d70c3a43ad2841ac235f6dc344c60fb (patch) | |
tree | 92923d2efccf90d1961071fa9acde59178a0d688 /drivers/gpu/nvgpu/lpwr/lpwr.h | |
parent | 505b442551a2e27aa3bc9e608c5a2bc9fccecbc4 (diff) | |
parent | 2aa3c85f8e82b3c07c39e677663abd3687c1822a (diff) |
Merge remote-tracking branch 'remotes/origin/dev/merge-nvgpu-t18x-into-nvgpu' into dev-kernel
Merge T186 - gp10b/gp106 code into common nvgpu repo
Bug 200266498
Change-Id: Ibf100ee38010cbed85c149b69b99147256f9a005
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/lpwr.h')
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/lpwr.h | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.h b/drivers/gpu/nvgpu/lpwr/lpwr.h new file mode 100644 index 00000000..6b3259df --- /dev/null +++ b/drivers/gpu/nvgpu/lpwr/lpwr.h | |||
@@ -0,0 +1,92 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _MSCG_H_ | ||
14 | #define _MSCG_H_ | ||
15 | |||
16 | #define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540 | ||
17 | |||
18 | #define NV_PMU_PG_PARAM_MCLK_CHANGE_MS_SWASR_ENABLED BIT(0x1) | ||
19 | #define NV_PMU_PG_PARAM_MCLK_CHANGE_GDDR5_WR_TRAINING_ENABLED BIT(0x3) | ||
20 | |||
21 | #define LPWR_ENTRY_COUNT_MAX 0x06 | ||
22 | |||
23 | #define LPWR_VBIOS_IDX_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) | ||
24 | |||
25 | #define LPWR_VBIOS_IDX_ENTRY_RSVD \ | ||
26 | (LPWR_VBIOS_IDX_ENTRY_COUNT_MAX - 1) | ||
27 | |||
28 | #define LPWR_VBIOS_BASE_SAMPLING_PERIOD_DEFAULT (500) | ||
29 | |||
30 | struct nvgpu_lpwr_bios_idx_entry { | ||
31 | u8 pcie_idx; | ||
32 | u8 gr_idx; | ||
33 | u8 ms_idx; | ||
34 | u8 di_idx; | ||
35 | u8 gc6_idx; | ||
36 | }; | ||
37 | |||
38 | struct nvgpu_lpwr_bios_idx_data { | ||
39 | u16 base_sampling_period; | ||
40 | struct nvgpu_lpwr_bios_idx_entry entry[LPWR_VBIOS_IDX_ENTRY_COUNT_MAX]; | ||
41 | }; | ||
42 | |||
43 | #define LPWR_VBIOS_MS_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) | ||
44 | |||
45 | struct nvgpu_lpwr_bios_ms_entry { | ||
46 | bool ms_enabled; | ||
47 | u32 feature_mask; | ||
48 | u32 asr_efficiency_thresholdl; | ||
49 | u16 dynamic_current_logic; | ||
50 | u16 dynamic_current_sram; | ||
51 | }; | ||
52 | |||
53 | struct nvgpu_lpwr_bios_ms_data { | ||
54 | u8 default_entry_idx; | ||
55 | u32 idle_threshold_us; | ||
56 | struct nvgpu_lpwr_bios_ms_entry entry[LPWR_VBIOS_MS_ENTRY_COUNT_MAX]; | ||
57 | }; | ||
58 | |||
59 | #define LPWR_VBIOS_GR_ENTRY_COUNT_MAX (LPWR_ENTRY_COUNT_MAX) | ||
60 | |||
61 | struct nvgpu_lpwr_bios_gr_entry { | ||
62 | bool gr_enabled; | ||
63 | u32 feature_mask; | ||
64 | }; | ||
65 | |||
66 | struct nvgpu_lpwr_bios_gr_data { | ||
67 | u8 default_entry_idx; | ||
68 | u32 idle_threshold_us; | ||
69 | u8 adaptive_gr_multiplier; | ||
70 | struct nvgpu_lpwr_bios_gr_entry entry[LPWR_VBIOS_GR_ENTRY_COUNT_MAX]; | ||
71 | }; | ||
72 | |||
73 | struct nvgpu_lpwr_bios_data { | ||
74 | struct nvgpu_lpwr_bios_idx_data idx; | ||
75 | struct nvgpu_lpwr_bios_ms_data ms; | ||
76 | struct nvgpu_lpwr_bios_gr_data gr; | ||
77 | }; | ||
78 | |||
79 | struct obj_lwpr { | ||
80 | struct nvgpu_lpwr_bios_data lwpr_bios_data; | ||
81 | u32 mclk_change_cache; | ||
82 | }; | ||
83 | |||
84 | u32 nvgpu_lpwr_pg_setup(struct gk20a *g); | ||
85 | int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate); | ||
86 | int nvgpu_lpwr_enable_pg(struct gk20a *g, bool pstate_lock); | ||
87 | int nvgpu_lpwr_disable_pg(struct gk20a *g, bool pstate_lock); | ||
88 | u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num); | ||
89 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); | ||
90 | u32 nvgpu_lpwr_post_init(struct gk20a *g); | ||
91 | |||
92 | #endif | ||