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| author | Deepak Nibade <dnibade@nvidia.com> | 2017-12-08 04:20:38 -0500 |
|---|---|---|
| committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-10 23:41:31 -0500 |
| commit | 5463b04f509c46131a729b62f0c0102fb7830b56 (patch) | |
| tree | 7f9c176db262acfee4cc2ea0de8fd8f1e1d9b8d0 /drivers/gpu/nvgpu/lpwr/lpwr.h | |
| parent | fa1b18c171aba0f8bb674ccc8c60ae81213a16f6 (diff) | |
gpu: nvgpu: fix gpc_tpc_mask setting for gv11b
Pre-gv11b we only had 2 TPCs in a GPC. But on gv11b we have 4 TPCs in a GPC.
Hence update gr_gv11b_set_gpc_tpc_mask() as per new configuration and allow
setting bits based on number of TPCs
Bug 2031635
Change-Id: I44f5f6ce5f3e2501c229c9fcda36fb330ebf8bd0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614044
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/lpwr.h')
0 files changed, 0 insertions, 0 deletions