diff options
author | smadhavan <smadhavan@nvidia.com> | 2018-09-14 02:28:41 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-25 00:17:42 -0400 |
commit | 3c3f80a687ae95c36341d9bf1753f63dfc4a06af (patch) | |
tree | 21f0c537bb7f417756e2c7feca17bdbcd0060702 /drivers/gpu/nvgpu/lpwr/lpwr.h | |
parent | 75e59e40045c6fbf93c5b828d8a12ba84b573585 (diff) |
gpu: nvgpu: MISRA Rule 21.2 header guard fixes
MISRA rule 21.2 doesn't allow the use of macro names which start with
an underscore. These leading underscores are to be removed from the
macro names. This patch will fix such violations in nvgpu by
renaming them to follow the convention,'NVGPU_PARENT-DIR_HEADER-NAME'
when there is no keyword repetition between file name and directory
or 'NVGPU_HEADER-NAME' when there is repetition.
JIRA NVGPU-1028
Change-Id: I8a473c6c1a864f3893920d8e06e305095e523d2a
Signed-off-by: smadhavan <smadhavan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809082
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Tested-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/lpwr.h')
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/lpwr.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.h b/drivers/gpu/nvgpu/lpwr/lpwr.h index 98b9769e..c38ba629 100644 --- a/drivers/gpu/nvgpu/lpwr/lpwr.h +++ b/drivers/gpu/nvgpu/lpwr/lpwr.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -19,8 +19,8 @@ | |||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | 19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
20 | * DEALINGS IN THE SOFTWARE. | 20 | * DEALINGS IN THE SOFTWARE. |
21 | */ | 21 | */ |
22 | #ifndef _MSCG_H_ | 22 | #ifndef NVGPU_LPWR_H |
23 | #define _MSCG_H_ | 23 | #define NVGPU_LPWR_H |
24 | 24 | ||
25 | #define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540 | 25 | #define MAX_SWASR_MCLK_FREQ_WITHOUT_WR_TRAINING_MAXWELL_MHZ 540 |
26 | 26 | ||
@@ -98,4 +98,4 @@ u32 nvgpu_lpwr_is_mscg_supported(struct gk20a *g, u32 pstate_num); | |||
98 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); | 98 | u32 nvgpu_lpwr_is_rppg_supported(struct gk20a *g, u32 pstate_num); |
99 | u32 nvgpu_lpwr_post_init(struct gk20a *g); | 99 | u32 nvgpu_lpwr_post_init(struct gk20a *g); |
100 | 100 | ||
101 | #endif | 101 | #endif /* NVGPU_LPWR_H */ |