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authorMahantesh Kumbar <mkumbar@nvidia.com>2017-07-04 01:55:00 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-05 03:39:21 -0400
commite808d345f11885453fc65862ec4e3dd4a375ff6d (patch)
treeccc3bb1ade5ff991ca1805084b76f154ca9736ee /drivers/gpu/nvgpu/lpwr/lpwr.c
parent2cf964d175abc0f3eae9ed0e01e6eeed5cd6b4da (diff)
gpu: nvgpu: rename gk20a_pmu_cmd_post()
- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/lpwr.c')
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 95eea2e3..c80ddee0 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -243,7 +243,7 @@ int nvgpu_lwpr_mclk_change(struct gk20a *g, u32 pstate)
243 cmd.cmd.pg.mclk_change.data = payload; 243 cmd.cmd.pg.mclk_change.data = payload;
244 244
245 nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE"); 245 nvgpu_pmu_dbg(g, "cmd post MS PMU_PG_PARAM_CMD_MCLK_CHANGE");
246 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, 246 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
247 PMU_COMMAND_QUEUE_HPQ, 247 PMU_COMMAND_QUEUE_HPQ,
248 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); 248 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
249 249
@@ -276,7 +276,7 @@ u32 nvgpu_lpwr_post_init(struct gk20a *g)
276 PMU_PG_PARAM_CMD_POST_INIT; 276 PMU_PG_PARAM_CMD_POST_INIT;
277 277
278 nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT"); 278 nvgpu_pmu_dbg(g, "cmd post post-init PMU_PG_PARAM_CMD_POST_INIT");
279 status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, 279 status = nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL,
280 PMU_COMMAND_QUEUE_LPQ, 280 PMU_COMMAND_QUEUE_LPQ,
281 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0); 281 nvgpu_pmu_handle_param_lpwr_msg, &ack_status, &seq, ~0);
282 282