summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/lpwr/lpwr.c
diff options
context:
space:
mode:
authorTerje Bergstrom <tbergstrom@nvidia.com>2017-02-09 11:17:47 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-17 16:46:32 -0500
commit53465def649b813987ca0d4a7ced744305204b82 (patch)
treecdff16681cb0442de3b1a8bd151b2a38c0bc5311 /drivers/gpu/nvgpu/lpwr/lpwr.c
parent29a79e6b80c6a0da489d8b0a470c86e2fec9c355 (diff)
gpu: nvgpu: Generalize BIOS code
Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in <nvgpu/bios.h> Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/lpwr/lpwr.c')
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c36
1 files changed, 14 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 1dc37cd2..9636891b 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -11,12 +11,13 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "gk20a/pmu_gk20a.h" 17#include "gk20a/pmu_gk20a.h"
16#include "gp106/pmu_gp106.h" 18#include "gp106/pmu_gp106.h"
17#include "gm206/bios_gm206.h" 19#include "gm206/bios_gm206.h"
18#include "pstate/pstate.h" 20#include "pstate/pstate.h"
19#include "include/bios.h"
20#include "perf/perf.h" 21#include "perf/perf.h"
21#include "lpwr.h" 22#include "lpwr.h"
22 23
@@ -30,13 +31,10 @@ static int get_lpwr_idx_table(struct gk20a *g)
30 struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 }; 31 struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 };
31 struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 }; 32 struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 };
32 33
33 if (g->ops.bios.get_perf_table_ptrs) { 34 lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
34 lpwr_idx_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, 35 g->bios.perf_token, LOWPOWER_TABLE);
35 g->bios.perf_token, LOWPOWER_TABLE); 36 if (lpwr_idx_table_ptr == NULL)
36 if (lpwr_idx_table_ptr == NULL) 37 return -EINVAL;
37 return -EINVAL;
38 } else
39 return -EINVAL;
40 38
41 memcpy(&header, lpwr_idx_table_ptr, 39 memcpy(&header, lpwr_idx_table_ptr,
42 sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header)); 40 sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header));
@@ -75,13 +73,10 @@ static int get_lpwr_gr_table(struct gk20a *g)
75 struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 }; 73 struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 };
76 struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 }; 74 struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 };
77 75
78 if (g->ops.bios.get_perf_table_ptrs) { 76 lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
79 lpwr_gr_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, 77 g->bios.perf_token, LOWPOWER_GR_TABLE);
80 g->bios.perf_token, LOWPOWER_GR_TABLE); 78 if (lpwr_gr_table_ptr == NULL)
81 if (lpwr_gr_table_ptr == NULL) 79 return -EINVAL;
82 return -EINVAL;
83 } else
84 return -EINVAL;
85 80
86 memcpy(&header, lpwr_gr_table_ptr, 81 memcpy(&header, lpwr_gr_table_ptr,
87 sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header)); 82 sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header));
@@ -122,13 +117,10 @@ static int get_lpwr_ms_table(struct gk20a *g)
122 struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 }; 117 struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 };
123 struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 }; 118 struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 };
124 119
125 if (g->ops.bios.get_perf_table_ptrs) { 120 lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
126 lpwr_ms_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, 121 g->bios.perf_token, LOWPOWER_MS_TABLE);
127 g->bios.perf_token, LOWPOWER_MS_TABLE); 122 if (lpwr_ms_table_ptr == NULL)
128 if (lpwr_ms_table_ptr == NULL) 123 return -EINVAL;
129 return -EINVAL;
130 } else
131 return -EINVAL;
132 124
133 memcpy(&header, lpwr_ms_table_ptr, 125 memcpy(&header, lpwr_ms_table_ptr,
134 sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header)); 126 sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header));