gpu: nvgpu: spew err for pbus interrupt

Spew err message for pri_squash, fecserr and pri_timeout
pbus interrupts. If FECS_TGT is set in timeout_save_0,
addr, write fields are not reliable. Also timeout_save_1
is unreliable. For both squash and timeout should have
correct data most of the time. Even for FECS_TGT, a timeout
for a read should indicate the correct transaction as Host
only supports one read at a time. It's mostly just writes
to FECS that have potentially incorrect information.

Bug 200246808
Bug 200350539

Change-Id: I8a992d924ff6c740a8dacecaaaf4ef257756d01d
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1568860
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
index 853227fe..f0dbfc30 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gk20a/hw_timer_gk20a.h
@@ -96,6 +96,18 @@ static inline u32 timer_pri_timeout_save_0_r(void)
 {
         return 0x00009084U;
 }
+static inline u32 timer_pri_timeout_save_0_fecs_tgt_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 timer_pri_timeout_save_0_addr_v(u32 r)
+{
+        return (r >> 2) & 0x3fffff;
+}
+static inline u32 timer_pri_timeout_save_0_write_v(u32 r)
+{
+        return (r >> 1) & 0x1;
+}
 static inline u32 timer_pri_timeout_save_1_r(void)
 {
         return 0x00009088U;