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authorDeepak Nibade <dnibade@nvidia.com>2017-06-07 05:23:58 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-06-15 08:43:48 -0400
commiteb8db3e4df159210ca9c7f834dbbc939a5c67a96 (patch)
treef11713d5af4ec8b58929505e5414c52b9482ca0a /drivers/gpu/nvgpu/include
parentf6c921ec97323c1eab7d3b8a0cda73abf041a00f (diff)
gpu: nvgpu: add APIs to export fuse offsets
Add below new APIs in common/linux/fuse.c and export them from include/nvgpu/fuse.h to read/write specific tegra fuse offsets void nvgpu_tegra_fuse_write_bypass(u32 val); void nvgpu_tegra_fuse_write_access_sw(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val); void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val); int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val); int nvgpu_tegra_fuse_read_reserved_calib(u32 *val); These APIs are needed to remove nvgpu's direct dependency on platform specific <soc/tegra/fuse.h> header Remove below generic APIs since they are no longer needed : nvgpu_tegra_fuse_read() nvgpu_tegra_fuse_write() Jira NVGPU-75 Change-Id: I366e6a3382f0c392b2132f4d3a7e286306bb2ec2 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/1497517 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/fuse.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/fuse.h b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
index 1e306b2d..3650fd58 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/fuse.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/fuse.h
@@ -13,9 +13,13 @@
13#ifndef __NVGPU_FUSE_H__ 13#ifndef __NVGPU_FUSE_H__
14#define __NVGPU_FUSE_H__ 14#define __NVGPU_FUSE_H__
15 15
16int nvgpu_tegra_fuse_read(unsigned long offset, u32 *value);
17void nvgpu_tegra_fuse_write(u32 value, unsigned long offset);
18
19int nvgpu_tegra_get_gpu_speedo_id(void); 16int nvgpu_tegra_get_gpu_speedo_id(void);
20 17
18void nvgpu_tegra_fuse_write_bypass(u32 val);
19void nvgpu_tegra_fuse_write_access_sw(u32 val);
20void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(u32 val);
21void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(u32 val);
22int nvgpu_tegra_fuse_read_gcplex_config_fuse(u32 *val);
23int nvgpu_tegra_fuse_read_reserved_calib(u32 *val);
24
21#endif 25#endif