diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-11-03 11:46:21 -0400 |
---|---|---|
committer | Deepak Nibade <dnibade@nvidia.com> | 2016-12-27 04:56:53 -0500 |
commit | e5824d8014c321fbe2c1e04e12307125dd50a472 (patch) | |
tree | 82657cd43c0dcd313b3251f3776e5e80b488fabc /drivers/gpu/nvgpu/include | |
parent | 62d13e613807e9bce3a9d1ef0c61725ef3a885ce (diff) |
gpu: nvgpu: MSCG support
- update gp106 pg engine init/list/features HALs
to support MS engine
- Added defines & interface for lpwr tables read from vbios.
- lpwr module which reads idx/gr/ms table from vbios to
map rppg/mscg support with respective p-state
- lpwr module public functions to control lpwr
features enable/disable mscg/rppg & mclk-change
request whenever change in mclk-change parameters
- lpwr public functions to know rppg/mscg support for
requested pstate,
- added mutex t prevent PG transition while arbiter
executes pstate transition
- nvgpu_clk_arb_get_current_pstate() of clk arbiter to
get current pstate
JIRA DNVGPU-71
Change-Id: Ifcd640cc19ef630be1e2a9ba07ec84023d8202a0
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1247553
(cherry picked from commit 8a441dea2410e1b5196ef24e56a7768b6980e46b)
Reviewed-on: http://git-master/r/1270989
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/bios.h | 64 |
1 files changed, 64 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h index f3939d14..097e90ec 100644 --- a/drivers/gpu/nvgpu/include/bios.h +++ b/drivers/gpu/nvgpu/include/bios.h | |||
@@ -925,4 +925,68 @@ struct vbios_fct_1x_entry { | |||
925 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) | 925 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_MASK GENMASK(31, 16) |
926 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 | 926 | #define NV_VBIOS_FCT_1X_ENTRY_PARAM8_FREQ_HYST_NEG_SHIFT 16 |
927 | 927 | ||
928 | /* LPWR Index Table */ | ||
929 | struct nvgpu_bios_lpwr_idx_table_1x_header { | ||
930 | u8 version; | ||
931 | u8 header_size; | ||
932 | u8 entry_size; | ||
933 | u8 entry_count; | ||
934 | u16 base_sampling_period; | ||
935 | } __packed; | ||
936 | |||
937 | struct nvgpu_bios_lpwr_idx_table_1x_entry { | ||
938 | u8 pcie_idx; | ||
939 | u8 gr_idx; | ||
940 | u8 ms_idx; | ||
941 | u8 di_idx; | ||
942 | u8 gc6_idx; | ||
943 | } __packed; | ||
944 | |||
945 | /* LPWR MS Table*/ | ||
946 | struct nvgpu_bios_lpwr_ms_table_1x_header { | ||
947 | u8 version; | ||
948 | u8 header_size; | ||
949 | u8 entry_size; | ||
950 | u8 entry_count; | ||
951 | u8 default_entry_idx; | ||
952 | u16 idle_threshold_us; | ||
953 | } __packed; | ||
954 | |||
955 | struct nvgpu_bios_lpwr_ms_table_1x_entry { | ||
956 | u32 feautre_mask; | ||
957 | u16 dynamic_current_logic; | ||
958 | u16 dynamic_current_sram; | ||
959 | } __packed; | ||
960 | |||
961 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_MASK GENMASK(0, 0) | ||
962 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SHIFT 0 | ||
963 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_MASK GENMASK(2, 2) | ||
964 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_SWASR_SHIFT 2 | ||
965 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_MASK \ | ||
966 | GENMASK(3, 3) | ||
967 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_CLOCK_GATING_SHIFT 3 | ||
968 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_MASK GENMASK(5, 5) | ||
969 | #define NV_VBIOS_LPWR_MS_FEATURE_MASK_MS_RPPG_SHIFT 5 | ||
970 | |||
971 | /* LPWR GR Table */ | ||
972 | struct nvgpu_bios_lpwr_gr_table_1x_header { | ||
973 | u8 version; | ||
974 | u8 header_size; | ||
975 | u8 entry_size; | ||
976 | u8 entry_count; | ||
977 | u8 default_entry_idx; | ||
978 | u16 idle_threshold_us; | ||
979 | u8 adaptive_gr_multiplier; | ||
980 | } __packed; | ||
981 | |||
982 | struct nvgpu_bios_lpwr_gr_table_1x_entry { | ||
983 | u32 feautre_mask; | ||
984 | } __packed; | ||
985 | |||
986 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_MASK GENMASK(0, 0) | ||
987 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_SHIFT 0 | ||
988 | |||
989 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) | ||
990 | #define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 | ||
991 | |||
928 | #endif | 992 | #endif |