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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-09-12 17:51:40 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-27 18:05:25 -0400
commite3ae03e17abd452c157545234348692364b4b9f6 (patch)
tree121b3dcde56c87f9a1008ad4f5effbeb69cff945 /drivers/gpu/nvgpu/include
parent78e3d22da3c2513d425c8c2560468ce854a982dd (diff)
gpu: nvgpu: Add MC APIs for reset masks
Add API for querying reset mask corresponding to a unit. The reset masks need to be read from MC HW header, and we do not want all units to access Mc HW headers themselves. JIRA NVGPU-954 Change-Id: I49ebbd891569de634bfc71afcecc8cd2358805c0 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823384 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gk20a.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/unit.h5
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 8627fddd..5a9c56e0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1156,7 +1156,7 @@ struct gpu_ops {
1156 void (*intr_mask)(struct gk20a *g); 1156 void (*intr_mask)(struct gk20a *g);
1157 void (*intr_enable)(struct gk20a *g); 1157 void (*intr_enable)(struct gk20a *g);
1158 void (*intr_unit_config)(struct gk20a *g, 1158 void (*intr_unit_config)(struct gk20a *g,
1159 bool enable, bool is_stalling, u32 unit); 1159 bool enable, bool is_stalling, u32 mask);
1160 void (*isr_stall)(struct gk20a *g); 1160 void (*isr_stall)(struct gk20a *g);
1161 bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); 1161 bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr);
1162 bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr); 1162 bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr);
@@ -1172,9 +1172,11 @@ struct gpu_ops {
1172 void (*enable)(struct gk20a *g, u32 units); 1172 void (*enable)(struct gk20a *g, u32 units);
1173 void (*disable)(struct gk20a *g, u32 units); 1173 void (*disable)(struct gk20a *g, u32 units);
1174 void (*reset)(struct gk20a *g, u32 units); 1174 void (*reset)(struct gk20a *g, u32 units);
1175 bool (*is_enabled)(struct gk20a *g, enum nvgpu_unit unit);
1175 bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1); 1176 bool (*is_intr1_pending)(struct gk20a *g, enum nvgpu_unit unit, u32 mc_intr_1);
1176 void (*log_pending_intrs)(struct gk20a *g); 1177 void (*log_pending_intrs)(struct gk20a *g);
1177 void (*fbpa_isr)(struct gk20a *g); 1178 void (*fbpa_isr)(struct gk20a *g);
1179 u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
1178 } mc; 1180 } mc;
1179 struct { 1181 struct {
1180 void (*show_dump)(struct gk20a *g, 1182 void (*show_dump)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/unit.h b/drivers/gpu/nvgpu/include/nvgpu/unit.h
index f919392e..11df652a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/unit.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/unit.h
@@ -31,6 +31,11 @@
31 */ 31 */
32enum nvgpu_unit { 32enum nvgpu_unit {
33 NVGPU_UNIT_FIFO, 33 NVGPU_UNIT_FIFO,
34 NVGPU_UNIT_PERFMON,
35 NVGPU_UNIT_GRAPH,
36 NVGPU_UNIT_BLG,
37 NVGPU_UNIT_PWR,
38 NVGPU_UNIT_NVDEC,
34}; 39};
35 40
36#endif /* NVGPU_UNIT_H */ 41#endif /* NVGPU_UNIT_H */