gpu: nvgpu: enable HWPM Mode-E context switch

- Write new pm mode to context buffer header. Ucode use
this mode to enable mode-e context switch. This is Mode-B
context switch of PMs with Mode-E streamout on one context.
If this mode is set, Ucode makes sure that Mode-E pipe
(perfmons, routers, pma) is idle before it context switches PMs.
- This allows us to collect counters in a secure way
(i.e. on context basis) with stream out.

Bug 2106999

Change-Id: I5a7435f09d1bf053ca428e538b0a57f3a175ac37
Signed-off-by: Vaibhav Kachore <vkachore@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1760366
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
index cd792835..b7f3df24 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_ctxsw_prog_gv100.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2017-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -144,6 +144,10 @@ static inline u32 ctxsw_prog_main_image_pm_mode_no_ctxsw_f(void)
 {
         return 0x0U;
 }
+static inline u32 ctxsw_prog_main_image_pm_mode_stream_out_ctxsw_f(void)
+{
+        return 0x2U;
+}
 static inline u32 ctxsw_prog_main_image_pm_smpc_mode_m(void)
 {
         return 0x7U << 3U;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index 6d05e44c..1eb26303 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -356,6 +356,7 @@ struct tegra_vgpu_fecs_trace_filter {
 enum {
         TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0,
         TEGRA_VGPU_CTXSW_MODE_CTXSW,
+        TEGRA_VGPU_CTXSW_MODE_STREAM_OUT_CTXSW,
 };
 
 enum {