gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl

Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.

Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.

Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.

Bug 2515097
But 2713590

Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
(cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 6 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/enabled.h b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
index fc7bab90..77b54ab9 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/enabled.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/enabled.h
@@ -181,10 +181,13 @@ struct gk20a;
 /* PLATFORM_ATOMIC support */
 #define NVGPU_SUPPORT_PLATFORM_ATOMIC           71
 
+/* NVGPU_GPU_IOCTL_SET_MMU_DEBUG_MODE is available */
+#define NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE    72
+
 /*
  * Must be greater than the largest bit offset in the above list.
  */
-#define NVGPU_MAX_ENABLED_BITS                  72
+#define NVGPU_MAX_ENABLED_BITS                  73U
 
 /**
  * nvgpu_is_enabled - Check if the passed flag is enabled.
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index a0af0c5c..f3a83602 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -529,6 +529,8 @@ struct gpu_ops {
                         u32 num_ppcs, u32 reg_list_ppc_count,
                         u32 *__offset_in_segment);
                 void (*set_debug_mode)(struct gk20a *g, bool enable);
+                int (*set_mmu_debug_mode)(struct gk20a *g,
+                        struct channel_gk20a *ch, bool enable);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);