gpu: nvgpu: common: fix MISRA 10.4 violations

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fix violations where an arithmetic operation is performed on
signed and unsigned int types.

Jira NVGPU-992

Change-Id: Iab512139a025e035ec82a9dd74245bcf1f3869fb
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1789425
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 64 insertions, 64 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
index 28374b9d..1240530f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h
@@ -84,21 +84,21 @@
 #define PMU_FALCON_REG_SIZE             (32)
 
 /* Choices for pmu_state */
-#define PMU_STATE_OFF                   0 /* PMU is off */
-#define PMU_STATE_STARTING              1 /* PMU is on, but not booted */
-#define PMU_STATE_INIT_RECEIVED         2 /* PMU init message received */
-#define PMU_STATE_ELPG_BOOTING          3 /* PMU is booting */
-#define PMU_STATE_ELPG_BOOTED           4 /* ELPG is initialized */
-#define PMU_STATE_LOADING_PG_BUF        5 /* Loading PG buf */
-#define PMU_STATE_LOADING_ZBC           6 /* Loading ZBC buf */
-#define PMU_STATE_STARTED               7 /* Fully unitialized */
-#define PMU_STATE_EXIT                  8 /* Exit PMU state machine */
-
-#define GK20A_PMU_UCODE_NB_MAX_OVERLAY      32
-#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH  64
-
-#define PMU_MAX_NUM_SEQUENCES           (256)
-#define PMU_SEQ_BIT_SHIFT               (5)
+#define PMU_STATE_OFF                   0U /* PMU is off */
+#define PMU_STATE_STARTING              1U /* PMU is on, but not booted */
+#define PMU_STATE_INIT_RECEIVED         2U /* PMU init message received */
+#define PMU_STATE_ELPG_BOOTING          3U /* PMU is booting */
+#define PMU_STATE_ELPG_BOOTED           4U /* ELPG is initialized */
+#define PMU_STATE_LOADING_PG_BUF        5U /* Loading PG buf */
+#define PMU_STATE_LOADING_ZBC           6U /* Loading ZBC buf */
+#define PMU_STATE_STARTED               7U /* Fully unitialized */
+#define PMU_STATE_EXIT                  8U /* Exit PMU state machine */
+
+#define GK20A_PMU_UCODE_NB_MAX_OVERLAY      32U
+#define GK20A_PMU_UCODE_NB_MAX_DATE_LENGTH  64U
+
+#define PMU_MAX_NUM_SEQUENCES           (256U)
+#define PMU_SEQ_BIT_SHIFT               (5U)
 #define PMU_SEQ_TBL_SIZE        \
                 (PMU_MAX_NUM_SEQUENCES >> PMU_SEQ_BIT_SHIFT)
 
@@ -132,8 +132,8 @@ enum {
 #define PMU_PG_LPWR_FEATURE_RPPG 0x0
 #define PMU_PG_LPWR_FEATURE_MSCG 0x1
 
-#define PMU_MSCG_DISABLED 0
-#define PMU_MSCG_ENABLED 1
+#define PMU_MSCG_DISABLED 0U
+#define PMU_MSCG_ENABLED 1U
 
 /* Default Sampling Period of AELPG */
 #define APCTRL_SAMPLING_PERIOD_PG_DEFAULT_US                    (1000000)
@@ -350,7 +350,7 @@ struct nvgpu_pmu {
         u32 mscg_stat;
         u32 mscg_transition_state;
 
-        int pmu_state;
+        u32 pmu_state;
 
 #define PMU_ELPG_ENABLE_ALLOW_DELAY_MSEC        1 /* msec */
         struct nvgpu_pg_init pg_init;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
index 68df80b4..e3317805 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_cmn.h
@@ -32,7 +32,7 @@
 #define PMU_COMMAND_QUEUE_LPQ           1U
 /* write by pmu, read by sw, accessed by interrupt handler, no lock */
 #define PMU_MESSAGE_QUEUE               4U
-#define PMU_QUEUE_COUNT                 5
+#define PMU_QUEUE_COUNT                 5U
 
 #define PMU_IS_COMMAND_QUEUE(id)        \
                 ((id)  < PMU_MESSAGE_QUEUE)
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
index 91e89365..ba6e9ec8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_perfmon.h
@@ -32,7 +32,7 @@
 #define PMU_PERFMON_FLAG_ENABLE_DECREASE        (0x00000002)
 #define PMU_PERFMON_FLAG_CLEAR_PREV             (0x00000004)
 
-#define NV_PMU_PERFMON_MAX_COUNTERS     10
+#define NV_PMU_PERFMON_MAX_COUNTERS     10U
 
 enum pmu_perfmon_cmd_start_fields {
         COUNTER_ALLOC
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
index 1ba9963c..c156a6c0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h
@@ -28,9 +28,9 @@
 /*PG defines*/
 
 /* Identifier for each PG */
-#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS (0x00000000)
-#define PMU_PG_ELPG_ENGINE_ID_MS       (0x00000004)
-#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE (0x00000005)
+#define PMU_PG_ELPG_ENGINE_ID_GRAPHICS          (0x00000000U)
+#define PMU_PG_ELPG_ENGINE_ID_MS                (0x00000004U)
+#define PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE    (0x00000005U)
 #define PMU_PG_ELPG_ENGINE_MAX    PMU_PG_ELPG_ENGINE_ID_INVALID_ENGINE
 
 /* PG message */
@@ -173,23 +173,23 @@ enum {
         SLOWDOWN_FACTOR_FPDIV_BYMAX,
 };
 
-#define PMU_PG_PARAM_CMD_GR_INIT_PARAM  0x0
-#define PMU_PG_PARAM_CMD_MS_INIT_PARAM  0x01
-#define PMU_PG_PARAM_CMD_MCLK_CHANGE  0x04
-#define PMU_PG_PARAM_CMD_POST_INIT  0x06
-#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE  0x07
-
-#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN     (1 << 0)
-#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING      (1 << 2)
-#define NVGPU_PMU_GR_FEATURE_MASK_RPPG              (1 << 3)
-#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING         (1 << 5)
-#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND            (1 << 6)
-#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE (1 << 7)
-#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY       (1 << 8)
-#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE       (1 << 9)
-#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM         (1 << 10)
-#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC        (1 << 11)
-#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG       (1 << 12)
+#define PMU_PG_PARAM_CMD_GR_INIT_PARAM                  0x0U
+#define PMU_PG_PARAM_CMD_MS_INIT_PARAM                  0x01U
+#define PMU_PG_PARAM_CMD_MCLK_CHANGE                    0x04U
+#define PMU_PG_PARAM_CMD_POST_INIT                      0x06U
+#define PMU_PG_PARAM_CMD_SUB_FEATURE_MASK_UPDATE        0x07U
+
+#define NVGPU_PMU_GR_FEATURE_MASK_SDIV_SLOWDOWN     BIT32(0)
+#define NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING      BIT32(2)
+#define NVGPU_PMU_GR_FEATURE_MASK_RPPG              BIT32(3)
+#define NVGPU_PMU_GR_FEATURE_MASK_PRIV_RING         BIT32(5)
+#define NVGPU_PMU_GR_FEATURE_MASK_UNBIND            BIT32(6)
+#define NVGPU_PMU_GR_FEATURE_MASK_SAVE_GLOBAL_STATE BIT32(7)
+#define NVGPU_PMU_GR_FEATURE_MASK_RESET_ENTRY       BIT32(8)
+#define NVGPU_PMU_GR_FEATURE_MASK_HW_SEQUENCE       BIT32(9)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_SRAM         BIT32(10)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_LOGIC        BIT32(11)
+#define NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG       BIT32(12)
 
 #define NVGPU_PMU_GR_FEATURE_MASK_ALL   \
         (       \
@@ -206,10 +206,10 @@ enum {
                 NVGPU_PMU_GR_FEATURE_MASK_ELPG_L2RPPG           \
         )
 
-#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  (1 << 0)
-#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR        (1 << 1)
-#define NVGPU_PMU_MS_FEATURE_MASK_RPPG          (1 << 8)
-#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING   (1 << 5)
+#define NVGPU_PMU_MS_FEATURE_MASK_CLOCK_GATING  BIT32(0)
+#define NVGPU_PMU_MS_FEATURE_MASK_SW_ASR        BIT32(1)
+#define NVGPU_PMU_MS_FEATURE_MASK_RPPG          BIT32(8)
+#define NVGPU_PMU_MS_FEATURE_MASK_FB_TRAINING   BIT32(5)
 
 #define NVGPU_PMU_MS_FEATURE_MASK_ALL   \
         (       \
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
index 1a05ec29..06486006 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
@@ -59,7 +59,7 @@ struct nv_pmu_rpc_cmd {
         u32 rpc_dmem_ptr;
 };
 
-#define NV_PMU_RPC_CMD_ID 0x80
+#define NV_PMU_RPC_CMD_ID 0x80U
 
 /* Message carrying the result of the RPC execution */
 struct nv_pmu_rpc_msg {
@@ -79,7 +79,7 @@ struct nv_pmu_rpc_msg {
         u32 rpc_dmem_ptr;
 };
 
-#define NV_PMU_RPC_MSG_ID 0x80
+#define NV_PMU_RPC_MSG_ID 0x80U
 
 struct pmu_cmd {
         struct pmu_hdr hdr;
@@ -116,26 +116,26 @@ struct pmu_msg {
         } msg;
 };
 
-#define PMU_UNIT_REWIND         (0x00)
-#define PMU_UNIT_PG                     (0x03)
-#define PMU_UNIT_INIT           (0x07)
-#define PMU_UNIT_ACR            (0x0A)
-#define PMU_UNIT_PERFMON_T18X   (0x11)
-#define PMU_UNIT_PERFMON        (0x12)
-#define PMU_UNIT_PERF           (0x13)
-#define PMU_UNIT_RC                     (0x1F)
-#define PMU_UNIT_FECS_MEM_OVERRIDE      (0x1E)
-#define PMU_UNIT_CLK    (0x0D)
-#define PMU_UNIT_THERM  (0x14)
-#define PMU_UNIT_PMGR   (0x18)
-#define PMU_UNIT_VOLT   (0x0E)
+#define PMU_UNIT_REWIND                 (0x00U)
+#define PMU_UNIT_PG                     (0x03U)
+#define PMU_UNIT_INIT                   (0x07U)
+#define PMU_UNIT_ACR                    (0x0AU)
+#define PMU_UNIT_PERFMON_T18X           (0x11U)
+#define PMU_UNIT_PERFMON                (0x12U)
+#define PMU_UNIT_PERF                   (0x13U)
+#define PMU_UNIT_RC                     (0x1FU)
+#define PMU_UNIT_FECS_MEM_OVERRIDE      (0x1EU)
+#define PMU_UNIT_CLK                    (0x0DU)
+#define PMU_UNIT_THERM                  (0x14U)
+#define PMU_UNIT_PMGR                   (0x18U)
+#define PMU_UNIT_VOLT                   (0x0EU)
 
-#define PMU_UNIT_END            (0x23)
-#define PMU_UNIT_INVALID        (0xFF)
+#define PMU_UNIT_END                    (0x23U)
+#define PMU_UNIT_INVALID                (0xFFU)
 
-#define PMU_UNIT_TEST_START     (0xFE)
-#define PMU_UNIT_END_SIM        (0xFF)
-#define PMU_UNIT_TEST_END       (0xFF)
+#define PMU_UNIT_TEST_START             (0xFEU)
+#define PMU_UNIT_END_SIM                (0xFFU)
+#define PMU_UNIT_TEST_END               (0xFFU)
 
 #define PMU_UNIT_ID_IS_VALID(id)                \
                 (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))