diff options
author | Konsta Holtta <kholtta@nvidia.com> | 2018-09-21 08:28:15 -0400 |
---|---|---|
committer | Konsta Holtta <kholtta@nvidia.com> | 2018-09-21 10:55:39 -0400 |
commit | ce5228e09411f9c54e96cfb0f7e9c857fd9b480d (patch) | |
tree | 26bbc69aa41fc1cb78746540cbf395f6a9cdda12 /drivers/gpu/nvgpu/include | |
parent | 84097d54f3b9ff242c4c3fb3c0a95353e8513b33 (diff) |
Revert "gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl"
This reverts commit c5810a670d367ae1dc405fcc3108e11265df34bb.
Bug 2400508
Jira VQRM-4806
Bug 200447406
Bug 2331747
Change-Id: Ie2a2c21f9285ff0349c7033fae24766a7117b462
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1837223
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 7 |
2 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 244b6ed2..39ab455b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -748,8 +748,6 @@ struct gpu_ops { | |||
748 | struct nvgpu_semaphore *s, u64 sema_va, | 748 | struct nvgpu_semaphore *s, u64 sema_va, |
749 | struct priv_cmd_entry *cmd, | 749 | struct priv_cmd_entry *cmd, |
750 | u32 off, bool acquire, bool wfi); | 750 | u32 off, bool acquire, bool wfi); |
751 | int (*set_sm_exception_type_mask)(struct channel_gk20a *ch, | ||
752 | u32 exception_mask); | ||
753 | } fifo; | 751 | } fifo; |
754 | struct pmu_v { | 752 | struct pmu_v { |
755 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 753 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 8ef5236c..f7a58c87 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -123,7 +123,6 @@ enum { | |||
123 | TEGRA_VGPU_CMD_RESUME = 83, | 123 | TEGRA_VGPU_CMD_RESUME = 83, |
124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, | 124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, |
125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, | 125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, |
126 | TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK = 86, | ||
127 | }; | 126 | }; |
128 | 127 | ||
129 | struct tegra_vgpu_connect_params { | 128 | struct tegra_vgpu_connect_params { |
@@ -468,11 +467,6 @@ struct tegra_vgpu_gpu_clk_rate_params { | |||
468 | u32 rate; /* in kHz */ | 467 | u32 rate; /* in kHz */ |
469 | }; | 468 | }; |
470 | 469 | ||
471 | struct tegra_vgpu_set_sm_exception_type_mask_params { | ||
472 | u64 handle; | ||
473 | u32 mask; | ||
474 | }; | ||
475 | |||
476 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | 470 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ |
477 | #define TEGRA_VGPU_MAX_ENGINES 4 | 471 | #define TEGRA_VGPU_MAX_ENGINES 4 |
478 | struct tegra_vgpu_engines_info { | 472 | struct tegra_vgpu_engines_info { |
@@ -684,7 +678,6 @@ struct tegra_vgpu_cmd_msg { | |||
684 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; | 678 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; |
685 | struct tegra_vgpu_ecc_info_params ecc_info; | 679 | struct tegra_vgpu_ecc_info_params ecc_info; |
686 | struct tegra_vgpu_ecc_counter_params ecc_counter; | 680 | struct tegra_vgpu_ecc_counter_params ecc_counter; |
687 | struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask; | ||
688 | char padding[192]; | 681 | char padding[192]; |
689 | } params; | 682 | } params; |
690 | }; | 683 | }; |