diff options
author | Alex Waterman <alexw@nvidia.com> | 2017-03-21 15:55:35 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-04-06 21:14:53 -0400 |
commit | c9665079d7b12f22a847c62587724b4ee120ca6e (patch) | |
tree | 7882bd08193db4c34b3b8ad7df7013339da2fba1 /drivers/gpu/nvgpu/include | |
parent | b69020bff5dfa69cad926c9374cdbe9a62509ffd (diff) |
gpu: nvgpu: rename mem_desc to nvgpu_mem
Renaming was done with the following command:
$ find -type f | \
xargs sed -i 's/struct mem_desc/struct nvgpu_mem/g'
Also rename mem_desc.[ch] to nvgpu_mem.[ch].
JIRA NVGPU-12
Change-Id: I69395758c22a56aa01e3dffbcded70a729bf559a
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1325547
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h (renamed from drivers/gpu/nvgpu/include/nvgpu/mem_desc.h) | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pramin.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/semaphore.h | 2 |
4 files changed, 26 insertions, 25 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h index f207c9ab..6991a0ba 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h +++ b/drivers/gpu/nvgpu/include/nvgpu/acr/nvgpu_acr.h | |||
@@ -67,8 +67,8 @@ struct wpr_carveout_info { | |||
67 | }; | 67 | }; |
68 | 68 | ||
69 | struct acr_desc { | 69 | struct acr_desc { |
70 | struct mem_desc ucode_blob; | 70 | struct nvgpu_mem ucode_blob; |
71 | struct mem_desc wpr_dummy; | 71 | struct nvgpu_mem wpr_dummy; |
72 | struct bin_hdr *bl_bin_hdr; | 72 | struct bin_hdr *bl_bin_hdr; |
73 | struct hsflcn_bl_desc *pmu_hsbl_desc; | 73 | struct hsflcn_bl_desc *pmu_hsbl_desc; |
74 | struct bin_hdr *hsbin_hdr; | 74 | struct bin_hdr *hsbin_hdr; |
@@ -79,9 +79,9 @@ struct acr_desc { | |||
79 | struct flcn_acr_desc *acr_dmem_desc; | 79 | struct flcn_acr_desc *acr_dmem_desc; |
80 | struct flcn_acr_desc_v1 *acr_dmem_desc_v1; | 80 | struct flcn_acr_desc_v1 *acr_dmem_desc_v1; |
81 | }; | 81 | }; |
82 | struct mem_desc acr_ucode; | 82 | struct nvgpu_mem acr_ucode; |
83 | const struct firmware *hsbl_fw; | 83 | const struct firmware *hsbl_fw; |
84 | struct mem_desc hsbl_ucode; | 84 | struct nvgpu_mem hsbl_ucode; |
85 | union { | 85 | union { |
86 | struct flcn_bl_dmem_desc bl_dmem_desc; | 86 | struct flcn_bl_dmem_desc bl_dmem_desc; |
87 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; | 87 | struct flcn_bl_dmem_desc_v1 bl_dmem_desc_v1; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h index 42d8854a..ae5dcc6e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h +++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h | |||
@@ -14,8 +14,8 @@ | |||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #ifndef __NVGPU_MEM_DESC_H__ | 17 | #ifndef __NVGPU_NVGPU_MEM_H__ |
18 | #define __NVGPU_MEM_DESC_H__ | 18 | #define __NVGPU_NVGPU_MEM_H__ |
19 | 19 | ||
20 | #include <linux/types.h> | 20 | #include <linux/types.h> |
21 | 21 | ||
@@ -38,7 +38,7 @@ enum nvgpu_aperture { | |||
38 | APERTURE_VIDMEM | 38 | APERTURE_VIDMEM |
39 | }; | 39 | }; |
40 | 40 | ||
41 | struct mem_desc { | 41 | struct nvgpu_mem { |
42 | void *cpu_va; /* sysmem only */ | 42 | void *cpu_va; /* sysmem only */ |
43 | struct page **pages; /* sysmem only */ | 43 | struct page **pages; /* sysmem only */ |
44 | struct sg_table *sgt; | 44 | struct sg_table *sgt; |
@@ -53,14 +53,15 @@ struct mem_desc { | |||
53 | unsigned long flags; | 53 | unsigned long flags; |
54 | }; | 54 | }; |
55 | 55 | ||
56 | static inline struct mem_desc * | 56 | static inline struct nvgpu_mem * |
57 | mem_desc_from_clear_list_entry(struct nvgpu_list_node *node) | 57 | nvgpu_mem_from_clear_list_entry(struct nvgpu_list_node *node) |
58 | { | 58 | { |
59 | return (struct mem_desc *) | 59 | return (struct nvgpu_mem *) |
60 | ((uintptr_t)node - offsetof(struct mem_desc, clear_list_entry)); | 60 | ((uintptr_t)node - offsetof(struct nvgpu_mem, |
61 | clear_list_entry)); | ||
61 | }; | 62 | }; |
62 | 63 | ||
63 | struct mem_desc_sub { | 64 | struct nvgpu_mem_sub { |
64 | u32 offset; | 65 | u32 offset; |
65 | u32 size; | 66 | u32 size; |
66 | }; | 67 | }; |
@@ -80,32 +81,32 @@ static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture) | |||
80 | * kernel mapping for this buffer. | 81 | * kernel mapping for this buffer. |
81 | */ | 82 | */ |
82 | 83 | ||
83 | int nvgpu_mem_begin(struct gk20a *g, struct mem_desc *mem); | 84 | int nvgpu_mem_begin(struct gk20a *g, struct nvgpu_mem *mem); |
84 | /* nop for null mem, like with free() or vunmap() */ | 85 | /* nop for null mem, like with free() or vunmap() */ |
85 | void nvgpu_mem_end(struct gk20a *g, struct mem_desc *mem); | 86 | void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem); |
86 | 87 | ||
87 | /* word-indexed offset */ | 88 | /* word-indexed offset */ |
88 | u32 nvgpu_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w); | 89 | u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w); |
89 | /* byte offset (32b-aligned) */ | 90 | /* byte offset (32b-aligned) */ |
90 | u32 nvgpu_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset); | 91 | u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset); |
91 | /* memcpy to cpu, offset and size in bytes (32b-aligned) */ | 92 | /* memcpy to cpu, offset and size in bytes (32b-aligned) */ |
92 | void nvgpu_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset, | 93 | void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, |
93 | void *dest, u32 size); | 94 | void *dest, u32 size); |
94 | 95 | ||
95 | /* word-indexed offset */ | 96 | /* word-indexed offset */ |
96 | void nvgpu_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data); | 97 | void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data); |
97 | /* byte offset (32b-aligned) */ | 98 | /* byte offset (32b-aligned) */ |
98 | void nvgpu_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data); | 99 | void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data); |
99 | /* memcpy from cpu, offset and size in bytes (32b-aligned) */ | 100 | /* memcpy from cpu, offset and size in bytes (32b-aligned) */ |
100 | void nvgpu_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, | 101 | void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, |
101 | void *src, u32 size); | 102 | void *src, u32 size); |
102 | /* size and offset in bytes (32b-aligned), filled with the constant byte c */ | 103 | /* size and offset in bytes (32b-aligned), filled with the constant byte c */ |
103 | void nvgpu_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, | 104 | void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, |
104 | u32 c, u32 size); | 105 | u32 c, u32 size); |
105 | 106 | ||
106 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, | 107 | u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture, |
107 | u32 sysmem_mask, u32 vidmem_mask); | 108 | u32 sysmem_mask, u32 vidmem_mask); |
108 | u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem, | 109 | u32 nvgpu_aperture_mask(struct gk20a *g, struct nvgpu_mem *mem, |
109 | u32 sysmem_mask, u32 vidmem_mask); | 110 | u32 sysmem_mask, u32 vidmem_mask); |
110 | 111 | ||
111 | #endif | 112 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pramin.h b/drivers/gpu/nvgpu/include/nvgpu/pramin.h index 7e0df06b..50367a6c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pramin.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pramin.h | |||
@@ -21,7 +21,7 @@ | |||
21 | 21 | ||
22 | struct gk20a; | 22 | struct gk20a; |
23 | struct mm_gk20a; | 23 | struct mm_gk20a; |
24 | struct mem_desc; | 24 | struct nvgpu_mem; |
25 | 25 | ||
26 | /* | 26 | /* |
27 | * This typedef is for functions that get called during the access_batched() | 27 | * This typedef is for functions that get called during the access_batched() |
@@ -37,7 +37,7 @@ void pramin_access_batch_rd_n(struct gk20a *g, u32 start, u32 words, u32 **arg); | |||
37 | void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg); | 37 | void pramin_access_batch_wr_n(struct gk20a *g, u32 start, u32 words, u32 **arg); |
38 | void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg); | 38 | void pramin_access_batch_set(struct gk20a *g, u32 start, u32 words, u32 **arg); |
39 | 39 | ||
40 | void nvgpu_pramin_access_batched(struct gk20a *g, struct mem_desc *mem, | 40 | void nvgpu_pramin_access_batched(struct gk20a *g, struct nvgpu_mem *mem, |
41 | u32 offset, u32 size, | 41 | u32 offset, u32 size, |
42 | pramin_access_batch_fn loop, u32 **arg); | 42 | pramin_access_batch_fn loop, u32 **arg); |
43 | 43 | ||
diff --git a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h index ade48178..d9120b65 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/semaphore.h +++ b/drivers/gpu/nvgpu/include/nvgpu/semaphore.h | |||
@@ -136,7 +136,7 @@ struct nvgpu_semaphore_sea { | |||
136 | struct page *pages[SEMAPHORE_POOL_COUNT]; | 136 | struct page *pages[SEMAPHORE_POOL_COUNT]; |
137 | */ | 137 | */ |
138 | 138 | ||
139 | struct mem_desc sea_mem; | 139 | struct nvgpu_mem sea_mem; |
140 | 140 | ||
141 | /* | 141 | /* |
142 | * Can't use a regular allocator here since the full range of pools are | 142 | * Can't use a regular allocator here since the full range of pools are |