gpu: nvgpu: refactor SET_SM_EXCEPTION_MASK ioctl

added hal layer for SM exception mask handling for
taking care of vitualization case.

Jira VQRM-4806
Bug  200447406
Bug  2331747

Change-Id: Ia44778a2e41c1a508c48026b8dee285966f1a544
Signed-off-by: aalex <aalex@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1816284
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 9 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 9799425e..a653109a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -748,6 +748,8 @@ struct gpu_ops {
                         struct nvgpu_semaphore *s, u64 sema_va,
                         struct priv_cmd_entry *cmd,
                         u32 off, bool acquire, bool wfi);
+                int (*set_sm_exception_type_mask)(struct channel_gk20a *ch,
+                                u32 exception_mask);
         } fifo;
         struct pmu_v {
                 u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
index f7a58c87..8ef5236c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h
@@ -123,6 +123,7 @@ enum {
         TEGRA_VGPU_CMD_RESUME = 83,
         TEGRA_VGPU_CMD_GET_ECC_INFO = 84,
         TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85,
+        TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK = 86,
 };
 
 struct tegra_vgpu_connect_params {
@@ -467,6 +468,11 @@ struct tegra_vgpu_gpu_clk_rate_params {
         u32 rate; /* in kHz */
 };
 
+struct tegra_vgpu_set_sm_exception_type_mask_params {
+        u64 handle;
+        u32 mask;
+};
+
 /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */
 #define TEGRA_VGPU_MAX_ENGINES                  4
 struct tegra_vgpu_engines_info {
@@ -678,6 +684,7 @@ struct tegra_vgpu_cmd_msg {
                 struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling;
                 struct tegra_vgpu_ecc_info_params ecc_info;
                 struct tegra_vgpu_ecc_counter_params ecc_counter;
+                struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask;
                 char padding[192];
         } params;
 };