diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-01-26 21:07:51 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-02-27 17:30:01 -0500 |
commit | c45462288d09955b2a163274d501c4d0aa10a74b (patch) | |
tree | fb76c9472df4b10af854d1c3a1e1159a846648dd /drivers/gpu/nvgpu/include | |
parent | 5025350b80f4ded30d6ab2ed3590c6a61937eef7 (diff) |
gpu: nvgpu: vgpu: move tegra_vgpu.h to include/nvgpu/vgpu/
tegra_vgpu.h is os agnostic, so move it out of linux folder.
Jira EVLR-2364
Change-Id: Ibbe8923f7af036b3b6730f682f5243ca73810f7b
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1649936
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 744 |
1 files changed, 744 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h new file mode 100644 index 00000000..78d64ebb --- /dev/null +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -0,0 +1,744 @@ | |||
1 | /* | ||
2 | * Tegra GPU Virtualization Interfaces to Server | ||
3 | * | ||
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef __TEGRA_VGPU_H | ||
26 | #define __TEGRA_VGPU_H | ||
27 | |||
28 | #include <nvgpu/types.h> | ||
29 | |||
30 | enum { | ||
31 | TEGRA_VGPU_MODULE_GPU = 0, | ||
32 | }; | ||
33 | |||
34 | enum { | ||
35 | /* Needs to follow last entry in TEGRA_VHOST_QUEUE_* list, | ||
36 | * in tegra_vhost.h | ||
37 | */ | ||
38 | TEGRA_VGPU_QUEUE_CMD = 3, | ||
39 | TEGRA_VGPU_QUEUE_INTR | ||
40 | }; | ||
41 | |||
42 | enum { | ||
43 | TEGRA_VGPU_CMD_CONNECT = 0, | ||
44 | TEGRA_VGPU_CMD_DISCONNECT = 1, | ||
45 | TEGRA_VGPU_CMD_ABORT = 2, | ||
46 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_HWCTX = 3, | ||
47 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWCTX = 4, | ||
48 | TEGRA_VGPU_CMD_GET_ATTRIBUTE = 5, | ||
49 | TEGRA_VGPU_CMD_MAP_BAR1 = 6, | ||
50 | TEGRA_VGPU_CMD_AS_ALLOC_SHARE = 7, | ||
51 | TEGRA_VGPU_CMD_AS_BIND_SHARE = 8, | ||
52 | TEGRA_VGPU_CMD_AS_FREE_SHARE = 9, | ||
53 | TEGRA_VGPU_CMD_AS_MAP = 10, | ||
54 | TEGRA_VGPU_CMD_AS_UNMAP = 11, | ||
55 | TEGRA_VGPU_CMD_CHANNEL_BIND = 13, | ||
56 | TEGRA_VGPU_CMD_CHANNEL_UNBIND = 14, | ||
57 | TEGRA_VGPU_CMD_CHANNEL_DISABLE = 15, | ||
58 | TEGRA_VGPU_CMD_CHANNEL_PREEMPT = 16, | ||
59 | TEGRA_VGPU_CMD_CHANNEL_SETUP_RAMFC = 17, | ||
60 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_CTX = 20, | ||
61 | TEGRA_VGPU_CMD_CHANNEL_ALLOC_GR_PATCH_CTX = 21, | ||
62 | TEGRA_VGPU_CMD_CHANNEL_FREE_GR_PATCH_CTX = 22, | ||
63 | TEGRA_VGPU_CMD_CHANNEL_MAP_GR_GLOBAL_CTX = 23, | ||
64 | TEGRA_VGPU_CMD_CHANNEL_UNMAP_GR_GLOBAL_CTX = 24, | ||
65 | TEGRA_VGPU_CMD_CHANNEL_COMMIT_GR_GLOBAL_CTX = 25, | ||
66 | TEGRA_VGPU_CMD_CHANNEL_LOAD_GR_GOLDEN_CTX = 26, | ||
67 | TEGRA_VGPU_CMD_CHANNEL_BIND_ZCULL = 27, | ||
68 | TEGRA_VGPU_CMD_CACHE_MAINT = 28, | ||
69 | TEGRA_VGPU_CMD_SUBMIT_RUNLIST = 29, | ||
70 | TEGRA_VGPU_CMD_GET_ZCULL_INFO = 30, | ||
71 | TEGRA_VGPU_CMD_ZBC_SET_TABLE = 31, | ||
72 | TEGRA_VGPU_CMD_ZBC_QUERY_TABLE = 32, | ||
73 | TEGRA_VGPU_CMD_AS_MAP_EX = 33, | ||
74 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTXSW_BUFFERS = 34, | ||
75 | TEGRA_VGPU_CMD_SET_MMU_DEBUG_MODE = 35, | ||
76 | TEGRA_VGPU_CMD_SET_SM_DEBUG_MODE = 36, | ||
77 | TEGRA_VGPU_CMD_REG_OPS = 37, | ||
78 | TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY = 38, | ||
79 | TEGRA_VGPU_CMD_CHANNEL_SET_RUNLIST_INTERLEAVE = 39, | ||
80 | TEGRA_VGPU_CMD_CHANNEL_SET_TIMESLICE = 40, | ||
81 | TEGRA_VGPU_CMD_FECS_TRACE_ENABLE = 41, | ||
82 | TEGRA_VGPU_CMD_FECS_TRACE_DISABLE = 42, | ||
83 | TEGRA_VGPU_CMD_FECS_TRACE_POLL = 43, | ||
84 | TEGRA_VGPU_CMD_FECS_TRACE_SET_FILTER = 44, | ||
85 | TEGRA_VGPU_CMD_CHANNEL_SET_SMPC_CTXSW_MODE = 45, | ||
86 | TEGRA_VGPU_CMD_CHANNEL_SET_HWPM_CTXSW_MODE = 46, | ||
87 | TEGRA_VGPU_CMD_CHANNEL_FREE_HWPM_CTX = 47, | ||
88 | TEGRA_VGPU_CMD_GR_CTX_ALLOC = 48, | ||
89 | TEGRA_VGPU_CMD_GR_CTX_FREE = 49, | ||
90 | TEGRA_VGPU_CMD_CHANNEL_BIND_GR_CTX = 50, | ||
91 | TEGRA_VGPU_CMD_TSG_BIND_GR_CTX = 51, | ||
92 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL = 52, | ||
93 | TEGRA_VGPU_CMD_TSG_UNBIND_CHANNEL = 53, | ||
94 | TEGRA_VGPU_CMD_TSG_PREEMPT = 54, | ||
95 | TEGRA_VGPU_CMD_TSG_SET_TIMESLICE = 55, | ||
96 | TEGRA_VGPU_CMD_TSG_SET_RUNLIST_INTERLEAVE = 56, | ||
97 | TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET = 57, | ||
98 | TEGRA_VGPU_CMD_CHANNEL_ENABLE = 58, | ||
99 | TEGRA_VGPU_CMD_READ_PTIMER = 59, | ||
100 | TEGRA_VGPU_CMD_SET_POWERGATE = 60, | ||
101 | TEGRA_VGPU_CMD_SET_GPU_CLK_RATE = 61, | ||
102 | TEGRA_VGPU_CMD_GET_CONSTANTS = 62, | ||
103 | TEGRA_VGPU_CMD_CHANNEL_CYCLESTATS_SNAPSHOT = 63, | ||
104 | TEGRA_VGPU_CMD_TSG_OPEN = 64, | ||
105 | TEGRA_VGPU_CMD_GET_GPU_LOAD = 65, | ||
106 | TEGRA_VGPU_CMD_SUSPEND_CONTEXTS = 66, | ||
107 | TEGRA_VGPU_CMD_RESUME_CONTEXTS = 67, | ||
108 | TEGRA_VGPU_CMD_CLEAR_SM_ERROR_STATE = 68, | ||
109 | TEGRA_VGPU_CMD_GET_GPU_CLK_RATE = 69, | ||
110 | TEGRA_VGPU_CMD_GET_GPU_FREQ_TABLE = 70, | ||
111 | TEGRA_VGPU_CMD_CAP_GPU_CLK_RATE = 71, | ||
112 | TEGRA_VGPU_CMD_PROF_MGT = 72, | ||
113 | TEGRA_VGPU_CMD_PERFBUF_MGT = 73, | ||
114 | TEGRA_VGPU_CMD_GET_TIMESTAMPS_ZIPPER = 74, | ||
115 | TEGRA_VGPU_CMD_TSG_RELEASE = 75, | ||
116 | TEGRA_VGPU_CMD_GET_VSMS_MAPPING = 76, | ||
117 | TEGRA_VGPU_CMD_ALLOC_CTX_HEADER = 77, | ||
118 | TEGRA_VGPU_CMD_FREE_CTX_HEADER = 78, | ||
119 | TEGRA_VGPU_CMD_MAP_SYNCPT = 79, | ||
120 | TEGRA_VGPU_CMD_TSG_BIND_CHANNEL_EX = 80, | ||
121 | }; | ||
122 | |||
123 | struct tegra_vgpu_connect_params { | ||
124 | u32 module; | ||
125 | u64 handle; | ||
126 | }; | ||
127 | |||
128 | struct tegra_vgpu_channel_hwctx_params { | ||
129 | u32 id; | ||
130 | u64 pid; | ||
131 | u64 handle; | ||
132 | }; | ||
133 | |||
134 | struct tegra_vgpu_attrib_params { | ||
135 | u32 attrib; | ||
136 | u32 value; | ||
137 | }; | ||
138 | |||
139 | struct tegra_vgpu_as_share_params { | ||
140 | u64 size; | ||
141 | u64 handle; | ||
142 | u32 big_page_size; | ||
143 | }; | ||
144 | |||
145 | struct tegra_vgpu_as_bind_share_params { | ||
146 | u64 as_handle; | ||
147 | u64 chan_handle; | ||
148 | }; | ||
149 | |||
150 | enum { | ||
151 | TEGRA_VGPU_MAP_PROT_NONE = 0, | ||
152 | TEGRA_VGPU_MAP_PROT_READ_ONLY, | ||
153 | TEGRA_VGPU_MAP_PROT_WRITE_ONLY | ||
154 | }; | ||
155 | |||
156 | struct tegra_vgpu_as_map_params { | ||
157 | u64 handle; | ||
158 | u64 addr; | ||
159 | u64 gpu_va; | ||
160 | u64 size; | ||
161 | u8 pgsz_idx; | ||
162 | u8 iova; | ||
163 | u8 kind; | ||
164 | u8 cacheable; | ||
165 | u8 clear_ctags; | ||
166 | u8 prot; | ||
167 | u32 ctag_offset; | ||
168 | }; | ||
169 | |||
170 | #define TEGRA_VGPU_MAP_CACHEABLE (1 << 0) | ||
171 | #define TEGRA_VGPU_MAP_IO_COHERENT (1 << 1) | ||
172 | #define TEGRA_VGPU_MAP_L3_ALLOC (1 << 2) | ||
173 | |||
174 | struct tegra_vgpu_as_map_ex_params { | ||
175 | u64 handle; | ||
176 | u64 gpu_va; | ||
177 | u64 size; | ||
178 | u32 mem_desc_count; | ||
179 | u8 pgsz_idx; | ||
180 | u8 iova; | ||
181 | u8 kind; | ||
182 | u32 flags; | ||
183 | u8 clear_ctags; | ||
184 | u8 prot; | ||
185 | u32 ctag_offset; | ||
186 | }; | ||
187 | |||
188 | struct tegra_vgpu_mem_desc { | ||
189 | u64 addr; | ||
190 | u64 length; | ||
191 | }; | ||
192 | |||
193 | struct tegra_vgpu_channel_config_params { | ||
194 | u64 handle; | ||
195 | }; | ||
196 | |||
197 | struct tegra_vgpu_ramfc_params { | ||
198 | u64 handle; | ||
199 | u64 gpfifo_va; | ||
200 | u32 num_entries; | ||
201 | u64 userd_addr; | ||
202 | u8 iova; | ||
203 | }; | ||
204 | |||
205 | struct tegra_vgpu_ch_ctx_params { | ||
206 | u64 handle; | ||
207 | u64 gr_ctx_va; | ||
208 | u64 patch_ctx_va; | ||
209 | u64 cb_va; | ||
210 | u64 attr_va; | ||
211 | u64 page_pool_va; | ||
212 | u64 priv_access_map_va; | ||
213 | u32 class_num; | ||
214 | }; | ||
215 | |||
216 | struct tegra_vgpu_zcull_bind_params { | ||
217 | u64 handle; | ||
218 | u64 zcull_va; | ||
219 | u32 mode; | ||
220 | }; | ||
221 | |||
222 | enum { | ||
223 | TEGRA_VGPU_L2_MAINT_FLUSH = 0, | ||
224 | TEGRA_VGPU_L2_MAINT_INV, | ||
225 | TEGRA_VGPU_L2_MAINT_FLUSH_INV, | ||
226 | TEGRA_VGPU_FB_FLUSH | ||
227 | }; | ||
228 | |||
229 | struct tegra_vgpu_cache_maint_params { | ||
230 | u8 op; | ||
231 | }; | ||
232 | |||
233 | struct tegra_vgpu_runlist_params { | ||
234 | u8 runlist_id; | ||
235 | u32 num_entries; | ||
236 | }; | ||
237 | |||
238 | struct tegra_vgpu_golden_ctx_params { | ||
239 | u32 size; | ||
240 | }; | ||
241 | |||
242 | struct tegra_vgpu_zcull_info_params { | ||
243 | u32 width_align_pixels; | ||
244 | u32 height_align_pixels; | ||
245 | u32 pixel_squares_by_aliquots; | ||
246 | u32 aliquot_total; | ||
247 | u32 region_byte_multiplier; | ||
248 | u32 region_header_size; | ||
249 | u32 subregion_header_size; | ||
250 | u32 subregion_width_align_pixels; | ||
251 | u32 subregion_height_align_pixels; | ||
252 | u32 subregion_count; | ||
253 | }; | ||
254 | |||
255 | #define TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE 4 | ||
256 | #define TEGRA_VGPU_ZBC_TYPE_INVALID 0 | ||
257 | #define TEGRA_VGPU_ZBC_TYPE_COLOR 1 | ||
258 | #define TEGRA_VGPU_ZBC_TYPE_DEPTH 2 | ||
259 | |||
260 | struct tegra_vgpu_zbc_set_table_params { | ||
261 | u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
262 | u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
263 | u32 depth; | ||
264 | u32 format; | ||
265 | u32 type; /* color or depth */ | ||
266 | }; | ||
267 | |||
268 | struct tegra_vgpu_zbc_query_table_params { | ||
269 | u32 color_ds[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
270 | u32 color_l2[TEGRA_VGPU_ZBC_COLOR_VALUE_SIZE]; | ||
271 | u32 depth; | ||
272 | u32 ref_cnt; | ||
273 | u32 format; | ||
274 | u32 type; /* color or depth */ | ||
275 | u32 index_size; /* [out] size, [in] index */ | ||
276 | }; | ||
277 | |||
278 | enum { | ||
279 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_MAIN, | ||
280 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_SPILL, | ||
281 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_PAGEPOOL, | ||
282 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_BETACB, | ||
283 | TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST | ||
284 | }; | ||
285 | |||
286 | enum { | ||
287 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_WFI, | ||
288 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_GFX_GFXP, | ||
289 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CTA, | ||
290 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_COMPUTE_CILP, | ||
291 | TEGRA_VGPU_GR_CTXSW_PREEMPTION_MODE_LAST | ||
292 | }; | ||
293 | |||
294 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params { | ||
295 | u64 handle; /* deprecated */ | ||
296 | u64 gpu_va[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; | ||
297 | u64 size[TEGRA_VGPU_GR_BIND_CTXSW_BUFFER_LAST]; | ||
298 | u32 mode; | ||
299 | u64 gr_ctx_handle; | ||
300 | }; | ||
301 | |||
302 | struct tegra_vgpu_mmu_debug_mode { | ||
303 | u32 enable; | ||
304 | }; | ||
305 | |||
306 | struct tegra_vgpu_sm_debug_mode { | ||
307 | u64 handle; | ||
308 | u64 sms; | ||
309 | u32 enable; | ||
310 | }; | ||
311 | |||
312 | struct tegra_vgpu_reg_op { | ||
313 | u8 op; | ||
314 | u8 type; | ||
315 | u8 status; | ||
316 | u8 quad; | ||
317 | u32 group_mask; | ||
318 | u32 sub_group_mask; | ||
319 | u32 offset; | ||
320 | u32 value_lo; | ||
321 | u32 value_hi; | ||
322 | u32 and_n_mask_lo; | ||
323 | u32 and_n_mask_hi; | ||
324 | }; | ||
325 | |||
326 | struct tegra_vgpu_reg_ops_params { | ||
327 | u64 handle; | ||
328 | u64 num_ops; | ||
329 | u32 is_profiler; | ||
330 | }; | ||
331 | |||
332 | struct tegra_vgpu_channel_priority_params { | ||
333 | u64 handle; | ||
334 | u32 priority; | ||
335 | }; | ||
336 | |||
337 | /* level follows nvgpu.h definitions */ | ||
338 | struct tegra_vgpu_channel_runlist_interleave_params { | ||
339 | u64 handle; | ||
340 | u32 level; | ||
341 | }; | ||
342 | |||
343 | struct tegra_vgpu_channel_timeslice_params { | ||
344 | u64 handle; | ||
345 | u32 timeslice_us; | ||
346 | }; | ||
347 | |||
348 | #define TEGRA_VGPU_FECS_TRACE_FILTER_SIZE 256 | ||
349 | struct tegra_vgpu_fecs_trace_filter { | ||
350 | u64 tag_bits[(TEGRA_VGPU_FECS_TRACE_FILTER_SIZE + 63) / 64]; | ||
351 | }; | ||
352 | |||
353 | enum { | ||
354 | TEGRA_VGPU_CTXSW_MODE_NO_CTXSW = 0, | ||
355 | TEGRA_VGPU_CTXSW_MODE_CTXSW, | ||
356 | }; | ||
357 | |||
358 | struct tegra_vgpu_channel_set_ctxsw_mode { | ||
359 | u64 handle; | ||
360 | u64 gpu_va; | ||
361 | u32 mode; | ||
362 | }; | ||
363 | |||
364 | struct tegra_vgpu_channel_free_hwpm_ctx { | ||
365 | u64 handle; | ||
366 | }; | ||
367 | |||
368 | struct tegra_vgpu_gr_ctx_params { | ||
369 | u64 gr_ctx_handle; | ||
370 | u64 as_handle; | ||
371 | u64 gr_ctx_va; | ||
372 | u32 class_num; | ||
373 | }; | ||
374 | |||
375 | struct tegra_vgpu_channel_bind_gr_ctx_params { | ||
376 | u64 ch_handle; | ||
377 | u64 gr_ctx_handle; | ||
378 | }; | ||
379 | |||
380 | struct tegra_vgpu_tsg_bind_gr_ctx_params { | ||
381 | u32 tsg_id; | ||
382 | u64 gr_ctx_handle; | ||
383 | }; | ||
384 | |||
385 | struct tegra_vgpu_tsg_bind_unbind_channel_params { | ||
386 | u32 tsg_id; | ||
387 | u64 ch_handle; | ||
388 | }; | ||
389 | |||
390 | struct tegra_vgpu_tsg_preempt_params { | ||
391 | u32 tsg_id; | ||
392 | }; | ||
393 | |||
394 | struct tegra_vgpu_tsg_timeslice_params { | ||
395 | u32 tsg_id; | ||
396 | u32 timeslice_us; | ||
397 | }; | ||
398 | |||
399 | struct tegra_vgpu_tsg_open_rel_params { | ||
400 | u32 tsg_id; | ||
401 | }; | ||
402 | |||
403 | /* level follows nvgpu.h definitions */ | ||
404 | struct tegra_vgpu_tsg_runlist_interleave_params { | ||
405 | u32 tsg_id; | ||
406 | u32 level; | ||
407 | }; | ||
408 | |||
409 | struct tegra_vgpu_read_ptimer_params { | ||
410 | u64 time; | ||
411 | }; | ||
412 | |||
413 | #define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT 16 | ||
414 | #define TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_SRC_ID_TSC 1 | ||
415 | struct tegra_vgpu_get_timestamps_zipper_params { | ||
416 | /* timestamp pairs */ | ||
417 | struct { | ||
418 | /* gpu timestamp value */ | ||
419 | u64 cpu_timestamp; | ||
420 | /* raw GPU counter (PTIMER) value */ | ||
421 | u64 gpu_timestamp; | ||
422 | } samples[TEGRA_VGPU_GET_TIMESTAMPS_ZIPPER_MAX_COUNT]; | ||
423 | /* number of pairs to read */ | ||
424 | u32 count; | ||
425 | /* cpu clock source id */ | ||
426 | u32 source_id; | ||
427 | }; | ||
428 | |||
429 | struct tegra_vgpu_set_powergate_params { | ||
430 | u32 mode; | ||
431 | }; | ||
432 | |||
433 | struct tegra_vgpu_gpu_clk_rate_params { | ||
434 | u32 rate; /* in kHz */ | ||
435 | }; | ||
436 | |||
437 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | ||
438 | #define TEGRA_VGPU_MAX_ENGINES 4 | ||
439 | struct tegra_vgpu_engines_info { | ||
440 | u32 num_engines; | ||
441 | struct engineinfo { | ||
442 | u32 engine_id; | ||
443 | u32 intr_mask; | ||
444 | u32 reset_mask; | ||
445 | u32 runlist_id; | ||
446 | u32 pbdma_id; | ||
447 | u32 inst_id; | ||
448 | u32 pri_base; | ||
449 | u32 engine_enum; | ||
450 | u32 fault_id; | ||
451 | } info[TEGRA_VGPU_MAX_ENGINES]; | ||
452 | }; | ||
453 | |||
454 | #define TEGRA_VGPU_MAX_GPC_COUNT 16 | ||
455 | #define TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC 16 | ||
456 | |||
457 | struct tegra_vgpu_constants_params { | ||
458 | u32 arch; | ||
459 | u32 impl; | ||
460 | u32 rev; | ||
461 | u32 max_freq; | ||
462 | u32 num_channels; | ||
463 | u32 golden_ctx_size; | ||
464 | u32 zcull_ctx_size; | ||
465 | u32 l2_size; | ||
466 | u32 ltc_count; | ||
467 | u32 cacheline_size; | ||
468 | u32 slices_per_ltc; | ||
469 | u32 comptags_per_cacheline; | ||
470 | u32 comptag_lines; | ||
471 | u32 sm_arch_sm_version; | ||
472 | u32 sm_arch_spa_version; | ||
473 | u32 sm_arch_warp_count; | ||
474 | u32 max_gpc_count; | ||
475 | u32 gpc_count; | ||
476 | u32 max_tpc_per_gpc_count; | ||
477 | u32 num_fbps; | ||
478 | u32 fbp_en_mask; | ||
479 | u32 ltc_per_fbp; | ||
480 | u32 max_lts_per_ltc; | ||
481 | u8 gpc_tpc_count[TEGRA_VGPU_MAX_GPC_COUNT]; | ||
482 | /* mask bits should be equal or larger than | ||
483 | * TEGRA_VGPU_MAX_TPC_COUNT_PER_GPC | ||
484 | */ | ||
485 | u16 gpc_tpc_mask[TEGRA_VGPU_MAX_GPC_COUNT]; | ||
486 | u32 hwpm_ctx_size; | ||
487 | u8 force_preempt_mode; | ||
488 | u32 default_timeslice_us; | ||
489 | u32 preempt_ctx_size; | ||
490 | u32 channel_base; | ||
491 | struct tegra_vgpu_engines_info engines_info; | ||
492 | u32 num_pce; | ||
493 | u32 sm_per_tpc; | ||
494 | u32 max_subctx_count; | ||
495 | }; | ||
496 | |||
497 | struct tegra_vgpu_channel_cyclestats_snapshot_params { | ||
498 | u64 handle; | ||
499 | u32 perfmon_start; | ||
500 | u32 perfmon_count; | ||
501 | u32 buf_info; /* client->srvr: get ptr; srvr->client: num pending */ | ||
502 | u8 subcmd; | ||
503 | u8 hw_overflow; | ||
504 | }; | ||
505 | |||
506 | struct tegra_vgpu_gpu_load_params { | ||
507 | u32 load; | ||
508 | }; | ||
509 | |||
510 | struct tegra_vgpu_suspend_resume_contexts { | ||
511 | u32 num_channels; | ||
512 | u16 resident_chid; | ||
513 | }; | ||
514 | |||
515 | struct tegra_vgpu_clear_sm_error_state { | ||
516 | u64 handle; | ||
517 | u32 sm_id; | ||
518 | }; | ||
519 | |||
520 | enum { | ||
521 | TEGRA_VGPU_PROF_GET_GLOBAL = 0, | ||
522 | TEGRA_VGPU_PROF_GET_CONTEXT, | ||
523 | TEGRA_VGPU_PROF_RELEASE | ||
524 | }; | ||
525 | |||
526 | struct tegra_vgpu_prof_mgt_params { | ||
527 | u32 mode; | ||
528 | }; | ||
529 | |||
530 | struct tegra_vgpu_perfbuf_mgt_params { | ||
531 | u64 vm_handle; | ||
532 | u64 offset; | ||
533 | u32 size; | ||
534 | }; | ||
535 | |||
536 | #define TEGRA_VGPU_GPU_FREQ_TABLE_SIZE 25 | ||
537 | |||
538 | struct tegra_vgpu_get_gpu_freq_table_params { | ||
539 | u32 num_freqs; | ||
540 | u32 freqs[TEGRA_VGPU_GPU_FREQ_TABLE_SIZE]; /* in kHz */ | ||
541 | }; | ||
542 | |||
543 | struct tegra_vgpu_vsms_mapping_params { | ||
544 | u32 num_sm; | ||
545 | }; | ||
546 | |||
547 | struct tegra_vgpu_vsms_mapping_entry { | ||
548 | u32 gpc_index; | ||
549 | u32 tpc_index; | ||
550 | u32 sm_index; | ||
551 | u32 global_tpc_index; | ||
552 | }; | ||
553 | |||
554 | struct tegra_vgpu_alloc_ctx_header_params { | ||
555 | u64 ch_handle; | ||
556 | u64 ctx_header_va; | ||
557 | }; | ||
558 | |||
559 | struct tegra_vgpu_free_ctx_header_params { | ||
560 | u64 ch_handle; | ||
561 | }; | ||
562 | |||
563 | struct tegra_vgpu_map_syncpt_params { | ||
564 | u64 as_handle; | ||
565 | u64 gpu_va; | ||
566 | u64 len; | ||
567 | u64 offset; | ||
568 | u8 prot; | ||
569 | }; | ||
570 | |||
571 | struct tegra_vgpu_tsg_bind_channel_ex_params { | ||
572 | u32 tsg_id; | ||
573 | u64 ch_handle; | ||
574 | u32 subctx_id; | ||
575 | u32 runqueue_sel; | ||
576 | }; | ||
577 | |||
578 | struct tegra_vgpu_cmd_msg { | ||
579 | u32 cmd; | ||
580 | int ret; | ||
581 | u64 handle; | ||
582 | union { | ||
583 | struct tegra_vgpu_connect_params connect; | ||
584 | struct tegra_vgpu_channel_hwctx_params channel_hwctx; | ||
585 | struct tegra_vgpu_attrib_params attrib; | ||
586 | struct tegra_vgpu_as_share_params as_share; | ||
587 | struct tegra_vgpu_as_bind_share_params as_bind_share; | ||
588 | struct tegra_vgpu_as_map_params as_map; | ||
589 | struct tegra_vgpu_as_map_ex_params as_map_ex; | ||
590 | struct tegra_vgpu_channel_config_params channel_config; | ||
591 | struct tegra_vgpu_ramfc_params ramfc; | ||
592 | struct tegra_vgpu_ch_ctx_params ch_ctx; | ||
593 | struct tegra_vgpu_zcull_bind_params zcull_bind; | ||
594 | struct tegra_vgpu_cache_maint_params cache_maint; | ||
595 | struct tegra_vgpu_runlist_params runlist; | ||
596 | struct tegra_vgpu_golden_ctx_params golden_ctx; | ||
597 | struct tegra_vgpu_zcull_info_params zcull_info; | ||
598 | struct tegra_vgpu_zbc_set_table_params zbc_set_table; | ||
599 | struct tegra_vgpu_zbc_query_table_params zbc_query_table; | ||
600 | struct tegra_vgpu_gr_bind_ctxsw_buffers_params gr_bind_ctxsw_buffers; | ||
601 | struct tegra_vgpu_mmu_debug_mode mmu_debug_mode; | ||
602 | struct tegra_vgpu_sm_debug_mode sm_debug_mode; | ||
603 | struct tegra_vgpu_reg_ops_params reg_ops; | ||
604 | struct tegra_vgpu_channel_priority_params channel_priority; | ||
605 | struct tegra_vgpu_channel_runlist_interleave_params channel_interleave; | ||
606 | struct tegra_vgpu_channel_timeslice_params channel_timeslice; | ||
607 | struct tegra_vgpu_fecs_trace_filter fecs_trace_filter; | ||
608 | struct tegra_vgpu_channel_set_ctxsw_mode set_ctxsw_mode; | ||
609 | struct tegra_vgpu_channel_free_hwpm_ctx free_hwpm_ctx; | ||
610 | struct tegra_vgpu_gr_ctx_params gr_ctx; | ||
611 | struct tegra_vgpu_channel_bind_gr_ctx_params ch_bind_gr_ctx; | ||
612 | struct tegra_vgpu_tsg_bind_gr_ctx_params tsg_bind_gr_ctx; | ||
613 | struct tegra_vgpu_tsg_bind_unbind_channel_params tsg_bind_unbind_channel; | ||
614 | struct tegra_vgpu_tsg_open_rel_params tsg_open; | ||
615 | struct tegra_vgpu_tsg_open_rel_params tsg_release; | ||
616 | struct tegra_vgpu_tsg_preempt_params tsg_preempt; | ||
617 | struct tegra_vgpu_tsg_timeslice_params tsg_timeslice; | ||
618 | struct tegra_vgpu_tsg_runlist_interleave_params tsg_interleave; | ||
619 | struct tegra_vgpu_read_ptimer_params read_ptimer; | ||
620 | struct tegra_vgpu_set_powergate_params set_powergate; | ||
621 | struct tegra_vgpu_gpu_clk_rate_params gpu_clk_rate; | ||
622 | struct tegra_vgpu_constants_params constants; | ||
623 | struct tegra_vgpu_channel_cyclestats_snapshot_params cyclestats_snapshot; | ||
624 | struct tegra_vgpu_gpu_load_params gpu_load; | ||
625 | struct tegra_vgpu_suspend_resume_contexts suspend_contexts; | ||
626 | struct tegra_vgpu_suspend_resume_contexts resume_contexts; | ||
627 | struct tegra_vgpu_clear_sm_error_state clear_sm_error_state; | ||
628 | struct tegra_vgpu_prof_mgt_params prof_management; | ||
629 | struct tegra_vgpu_perfbuf_mgt_params perfbuf_management; | ||
630 | struct tegra_vgpu_get_timestamps_zipper_params get_timestamps_zipper; | ||
631 | struct tegra_vgpu_get_gpu_freq_table_params get_gpu_freq_table; | ||
632 | struct tegra_vgpu_vsms_mapping_params vsms_mapping; | ||
633 | struct tegra_vgpu_alloc_ctx_header_params alloc_ctx_header; | ||
634 | struct tegra_vgpu_free_ctx_header_params free_ctx_header; | ||
635 | struct tegra_vgpu_map_syncpt_params map_syncpt; | ||
636 | struct tegra_vgpu_tsg_bind_channel_ex_params tsg_bind_channel_ex; | ||
637 | char padding[192]; | ||
638 | } params; | ||
639 | }; | ||
640 | |||
641 | enum { | ||
642 | TEGRA_VGPU_GR_INTR_NOTIFY = 0, | ||
643 | TEGRA_VGPU_GR_INTR_SEMAPHORE_TIMEOUT = 1, | ||
644 | TEGRA_VGPU_GR_INTR_ILLEGAL_NOTIFY = 2, | ||
645 | TEGRA_VGPU_GR_INTR_ILLEGAL_METHOD = 3, | ||
646 | TEGRA_VGPU_GR_INTR_ILLEGAL_CLASS = 4, | ||
647 | TEGRA_VGPU_GR_INTR_FECS_ERROR = 5, | ||
648 | TEGRA_VGPU_GR_INTR_CLASS_ERROR = 6, | ||
649 | TEGRA_VGPU_GR_INTR_FIRMWARE_METHOD = 7, | ||
650 | TEGRA_VGPU_GR_INTR_EXCEPTION = 8, | ||
651 | TEGRA_VGPU_GR_INTR_SEMAPHORE = 9, | ||
652 | TEGRA_VGPU_FIFO_INTR_PBDMA = 10, | ||
653 | TEGRA_VGPU_FIFO_INTR_CTXSW_TIMEOUT = 11, | ||
654 | TEGRA_VGPU_FIFO_INTR_MMU_FAULT = 12, | ||
655 | TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE = 13, | ||
656 | TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL = 14, | ||
657 | TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE = 15, | ||
658 | TEGRA_VGPU_GR_INTR_SM_EXCEPTION = 16, | ||
659 | }; | ||
660 | |||
661 | struct tegra_vgpu_gr_intr_info { | ||
662 | u32 type; | ||
663 | u32 chid; | ||
664 | }; | ||
665 | |||
666 | struct tegra_vgpu_gr_nonstall_intr_info { | ||
667 | u32 type; | ||
668 | }; | ||
669 | |||
670 | struct tegra_vgpu_fifo_intr_info { | ||
671 | u32 type; | ||
672 | u32 chid; | ||
673 | }; | ||
674 | |||
675 | struct tegra_vgpu_fifo_nonstall_intr_info { | ||
676 | u32 type; | ||
677 | }; | ||
678 | |||
679 | struct tegra_vgpu_ce2_nonstall_intr_info { | ||
680 | u32 type; | ||
681 | }; | ||
682 | |||
683 | enum { | ||
684 | TEGRA_VGPU_FECS_TRACE_DATA_UPDATE = 0 | ||
685 | }; | ||
686 | |||
687 | struct tegra_vgpu_fecs_trace_event_info { | ||
688 | u32 type; | ||
689 | }; | ||
690 | |||
691 | struct tegra_vgpu_channel_event_info { | ||
692 | u32 event_id; | ||
693 | u32 is_tsg; | ||
694 | u32 id; /* channel id or tsg id */ | ||
695 | }; | ||
696 | |||
697 | struct tegra_vgpu_sm_esr_info { | ||
698 | u32 sm_id; | ||
699 | u32 hww_global_esr; | ||
700 | u32 hww_warp_esr; | ||
701 | u64 hww_warp_esr_pc; | ||
702 | u32 hww_global_esr_report_mask; | ||
703 | u32 hww_warp_esr_report_mask; | ||
704 | }; | ||
705 | |||
706 | enum { | ||
707 | |||
708 | TEGRA_VGPU_INTR_GR = 0, | ||
709 | TEGRA_VGPU_INTR_FIFO = 1, | ||
710 | TEGRA_VGPU_INTR_CE2 = 2, | ||
711 | TEGRA_VGPU_NONSTALL_INTR_GR = 3, | ||
712 | TEGRA_VGPU_NONSTALL_INTR_FIFO = 4, | ||
713 | TEGRA_VGPU_NONSTALL_INTR_CE2 = 5, | ||
714 | }; | ||
715 | |||
716 | enum { | ||
717 | TEGRA_VGPU_EVENT_INTR = 0, | ||
718 | TEGRA_VGPU_EVENT_ABORT = 1, | ||
719 | TEGRA_VGPU_EVENT_FECS_TRACE = 2, | ||
720 | TEGRA_VGPU_EVENT_CHANNEL = 3, | ||
721 | TEGRA_VGPU_EVENT_SM_ESR = 4, | ||
722 | }; | ||
723 | |||
724 | struct tegra_vgpu_intr_msg { | ||
725 | unsigned int event; | ||
726 | u32 unit; | ||
727 | union { | ||
728 | struct tegra_vgpu_gr_intr_info gr_intr; | ||
729 | struct tegra_vgpu_gr_nonstall_intr_info gr_nonstall_intr; | ||
730 | struct tegra_vgpu_fifo_intr_info fifo_intr; | ||
731 | struct tegra_vgpu_fifo_nonstall_intr_info fifo_nonstall_intr; | ||
732 | struct tegra_vgpu_ce2_nonstall_intr_info ce2_nonstall_intr; | ||
733 | struct tegra_vgpu_fecs_trace_event_info fecs_trace; | ||
734 | struct tegra_vgpu_channel_event_info channel_event; | ||
735 | struct tegra_vgpu_sm_esr_info sm_esr; | ||
736 | char padding[32]; | ||
737 | } info; | ||
738 | }; | ||
739 | |||
740 | #define TEGRA_VGPU_QUEUE_SIZES \ | ||
741 | 512, \ | ||
742 | sizeof(struct tegra_vgpu_intr_msg) | ||
743 | |||
744 | #endif | ||