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authorAlex Waterman <alexw@nvidia.com>2017-03-15 19:42:12 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-06 21:14:48 -0400
commitb69020bff5dfa69cad926c9374cdbe9a62509ffd (patch)
tree222f6b6bc23561a38004a257cbac401e431ff3be /drivers/gpu/nvgpu/include
parentfa4ecf5730a75269e85cc41c2ad2ee61307e72a9 (diff)
gpu: nvgpu: Rename gk20a_mem_* functions
Rename the functions used for mem_desc access to nvgpu_mem_*. JIRA NVGPU-12 Change-Id: Ibfdc1112d43f0a125e4487c250e3f977ffd2cd75 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1323325 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/include')
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/mem_desc.h30
1 files changed, 15 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h b/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h
index 528fd7bc..42d8854a 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/mem_desc.h
@@ -28,11 +28,11 @@ struct gk20a;
28struct nvgpu_allocator; 28struct nvgpu_allocator;
29 29
30/* 30/*
31 * Real location of a buffer - gk20a_aperture_mask() will deduce what will be 31 * Real location of a buffer - nvgpu_aperture_mask() will deduce what will be
32 * told to the gpu about the aperture, but this flag designates where the 32 * told to the gpu about the aperture, but this flag designates where the
33 * memory actually was allocated from. 33 * memory actually was allocated from.
34 */ 34 */
35enum gk20a_aperture { 35enum nvgpu_aperture {
36 APERTURE_INVALID, /* unallocated or N/A */ 36 APERTURE_INVALID, /* unallocated or N/A */
37 APERTURE_SYSMEM, 37 APERTURE_SYSMEM,
38 APERTURE_VIDMEM 38 APERTURE_VIDMEM
@@ -42,7 +42,7 @@ struct mem_desc {
42 void *cpu_va; /* sysmem only */ 42 void *cpu_va; /* sysmem only */
43 struct page **pages; /* sysmem only */ 43 struct page **pages; /* sysmem only */
44 struct sg_table *sgt; 44 struct sg_table *sgt;
45 enum gk20a_aperture aperture; 45 enum nvgpu_aperture aperture;
46 size_t size; 46 size_t size;
47 u64 gpu_va; 47 u64 gpu_va;
48 bool fixed; /* vidmem only */ 48 bool fixed; /* vidmem only */
@@ -65,7 +65,7 @@ struct mem_desc_sub {
65 u32 size; 65 u32 size;
66}; 66};
67 67
68static inline const char *gk20a_aperture_str(enum gk20a_aperture aperture) 68static inline const char *nvgpu_aperture_str(enum nvgpu_aperture aperture)
69{ 69{
70 switch (aperture) { 70 switch (aperture) {
71 case APERTURE_INVALID: return "invalid"; 71 case APERTURE_INVALID: return "invalid";
@@ -80,32 +80,32 @@ static inline const char *gk20a_aperture_str(enum gk20a_aperture aperture)
80 * kernel mapping for this buffer. 80 * kernel mapping for this buffer.
81 */ 81 */
82 82
83int gk20a_mem_begin(struct gk20a *g, struct mem_desc *mem); 83int nvgpu_mem_begin(struct gk20a *g, struct mem_desc *mem);
84/* nop for null mem, like with free() or vunmap() */ 84/* nop for null mem, like with free() or vunmap() */
85void gk20a_mem_end(struct gk20a *g, struct mem_desc *mem); 85void nvgpu_mem_end(struct gk20a *g, struct mem_desc *mem);
86 86
87/* word-indexed offset */ 87/* word-indexed offset */
88u32 gk20a_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w); 88u32 nvgpu_mem_rd32(struct gk20a *g, struct mem_desc *mem, u32 w);
89/* byte offset (32b-aligned) */ 89/* byte offset (32b-aligned) */
90u32 gk20a_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset); 90u32 nvgpu_mem_rd(struct gk20a *g, struct mem_desc *mem, u32 offset);
91/* memcpy to cpu, offset and size in bytes (32b-aligned) */ 91/* memcpy to cpu, offset and size in bytes (32b-aligned) */
92void gk20a_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset, 92void nvgpu_mem_rd_n(struct gk20a *g, struct mem_desc *mem, u32 offset,
93 void *dest, u32 size); 93 void *dest, u32 size);
94 94
95/* word-indexed offset */ 95/* word-indexed offset */
96void gk20a_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data); 96void nvgpu_mem_wr32(struct gk20a *g, struct mem_desc *mem, u32 w, u32 data);
97/* byte offset (32b-aligned) */ 97/* byte offset (32b-aligned) */
98void gk20a_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data); 98void nvgpu_mem_wr(struct gk20a *g, struct mem_desc *mem, u32 offset, u32 data);
99/* memcpy from cpu, offset and size in bytes (32b-aligned) */ 99/* memcpy from cpu, offset and size in bytes (32b-aligned) */
100void gk20a_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset, 100void nvgpu_mem_wr_n(struct gk20a *g, struct mem_desc *mem, u32 offset,
101 void *src, u32 size); 101 void *src, u32 size);
102/* size and offset in bytes (32b-aligned), filled with the constant byte c */ 102/* size and offset in bytes (32b-aligned), filled with the constant byte c */
103void gk20a_memset(struct gk20a *g, struct mem_desc *mem, u32 offset, 103void nvgpu_memset(struct gk20a *g, struct mem_desc *mem, u32 offset,
104 u32 c, u32 size); 104 u32 c, u32 size);
105 105
106u32 __gk20a_aperture_mask(struct gk20a *g, enum gk20a_aperture aperture, 106u32 __nvgpu_aperture_mask(struct gk20a *g, enum nvgpu_aperture aperture,
107 u32 sysmem_mask, u32 vidmem_mask); 107 u32 sysmem_mask, u32 vidmem_mask);
108u32 gk20a_aperture_mask(struct gk20a *g, struct mem_desc *mem, 108u32 nvgpu_aperture_mask(struct gk20a *g, struct mem_desc *mem,
109 u32 sysmem_mask, u32 vidmem_mask); 109 u32 sysmem_mask, u32 vidmem_mask);
110 110
111#endif 111#endif