gpu: nvgpu: Use TPC_PG_MASK to powergate the TPC

- In GV11B, read fuse_status_opt_tpc_gpc register
  to read which TPCs are floorswept.
- The driver will also read sysfs node: tpc_pg_mask
- Based on these two values "can_tpc_powergate" will
  be set to true or false and mask will be used to write to
  fuse_ctrl_opt_tpc_gpc register to powergate the TPC.
- can_tpc_powergate = true indicates that the mask value
  sent from userspace is valid and can be used to power gate
  the desired TPC
- can_tpc_powergate = false indicates that the mask value
  sent from userspace is not valid and cannot  be used to
  power gate the desired TPC.

Bug 200532639

Change-Id: Ib0806e4c96305a13b3574e8063ad8e16770aa7cd
Signed-off-by: Divya Singhatwaria <dsinghatwari@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2159219
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 5 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 7ed4c714..c9002f47 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -149,7 +149,7 @@ enum gk20a_cbc_op {
 
 #define nvgpu_get_litter_value(g, v) (g)->ops.get_litter_value((g), v)
 
-#define MAX_TPC_PG_CONFIGS      3
+#define MAX_TPC_PG_CONFIGS      9
 
 enum nvgpu_unit;
 
@@ -1348,6 +1348,9 @@ struct gpu_ops {
         struct {
                 void (*acr_sw_init)(struct gk20a *g, struct nvgpu_acr *acr);
         } acr;
+        struct {
+                int (*tpc_powergate)(struct gk20a *g, u32 fuse_status);
+        } tpc;
         void (*semaphore_wakeup)(struct gk20a *g, bool post_events);
 };
 
@@ -1615,6 +1618,7 @@ struct gk20a {
         u32 tpc_fs_mask_user;
 
         u32 tpc_pg_mask;
+        u32 tpc_count;
         bool can_tpc_powergate;
 
         u32 valid_tpc_mask[MAX_TPC_PG_CONFIGS];