gpu:nvgpu: Update number of LUT entries

CTRL_CLK_LUT_NUM_ENTRIES to 128
And fix build issues that appeared with 128 entries.

Bug 2331655

Change-Id: If116bff14be9a1923e075f783fdb9a2e992208b8
Signed-off-by: Vaikundanathan S <vaikuns@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1810493
Reviewed-on: https://git-master.nvidia.com/r/1813861
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 3 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index e2a0cbf7..9799425e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -852,7 +852,7 @@ struct gpu_ops {
                                 (struct gk20a *g,
                                 struct boardobjgrp *pboardobjgrp,
                                 struct boardobjgrp_pmu_cmd *cmd, u8 id, u8 msgid,
-                                u8 hdrsize, u8 entrysize, u16 fbsize, u32 ss_offset,
+                                u16 hdrsize, u16 entrysize, u16 fbsize, u32 ss_offset,
                                 u8 rpc_func_id);
                         int (*boardobjgrp_pmuset_impl)(struct gk20a *g,
                                 struct boardobjgrp *pboardobjgrp);
@@ -1113,6 +1113,7 @@ struct gpu_ops {
                 bool support_pmgr_domain;
                 bool support_lpwr_pg;
                 u32 (*perf_pmu_vfe_load)(struct gk20a *g);
+                u32 lut_num_entries;
         } clk;
         struct {
                 int (*arbiter_clk_init)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
index c9a2750f..b0f9e101 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmu_super_surf_if.h
@@ -56,7 +56,6 @@ struct nv_pmu_super_surface {
                 struct nv_pmu_clk_clk_vf_point_boardobj_grp_set clk_vf_point_grp_set;
                 struct nv_pmu_clk_clk_vin_device_boardobj_grp_get_status clk_vin_device_grp_get_status;
                 struct nv_pmu_clk_clk_fll_device_boardobj_grp_get_status clk_fll_device_grp_get_status;
-                u8 clk_rsvd1[0x800];
                 struct nv_pmu_clk_clk_vf_point_boardobj_grp_get_status clk_vf_point_grp_get_status;
                 u8 clk_rsvd[0x4660];
         } clk;
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
index b94db25c..70a913b6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifclk.h
@@ -560,7 +560,7 @@ struct nv_pmu_clk_clk_fll_device_boardobj_get_status {
         u8 current_regime_id;
         bool b_dvco_min_reached;
         u16 min_freq_mhz;
-        struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES, 2)];
+        struct nv_pmu_clk_lut_vf_entry lut_vf_curve[NV_UNSIGNED_ROUNDED_DIV(CTRL_CLK_LUT_NUM_ENTRIES_MAX, 2)];
 };
 
 union nv_pmu_clk_clk_fll_device_boardobj_get_status_union {